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<p>Declaring the components (<a class="el" href="class_s_y_c0001a.html">SYC0001a</a>, <a class="el" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html">SERIALMASTER</a>, <a class="el" href="classuart__wishbone__slave.html">uart_wishbone_slave</a>)
<a href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#details">More...</a></p>
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<table class="memberdecls">
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Components</h2></td></tr>
<tr class="memitem:a99b85cc71dbbaa06e16f4d4351530462"><td class="memItemLeft" align="right" valign="top"><a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a99b85cc71dbbaa06e16f4d4351530462">SYC0001a</a> </td><td class="memItemRight" valign="bottom"> <b></b> <em><a class="el" href="class_s_y_c0001a.html"><Entity SYC0001a> </a></em></td></tr>
<tr class="memdesc:a99b85cc71dbbaa06e16f4d4351530462"><td class="mdescLeft"> </td><td class="mdescRight">Clock output. <a href="#a99b85cc71dbbaa06e16f4d4351530462"></a><br/></td></tr>
<tr class="memitem:a3eba7772cc5be92821da2ebda4b73fae"><td class="memItemLeft" align="right" valign="top"><a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a3eba7772cc5be92821da2ebda4b73fae">SERIALMASTER</a> </td><td class="memItemRight" valign="bottom"> <b></b> <em><a class="el" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html"><Entity SERIALMASTER> </a></em></td></tr>
<tr class="memdesc:a3eba7772cc5be92821da2ebda4b73fae"><td class="mdescLeft"> </td><td class="mdescRight">Ack input. <a href="#a3eba7772cc5be92821da2ebda4b73fae"></a><br/></td></tr>
<tr class="memitem:abc849ae7612bb6c8206d5bb023aee9b7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#abc849ae7612bb6c8206d5bb023aee9b7">uart_wishbone_slave</a> </td><td class="memItemRight" valign="bottom"> <b></b> <em><a class="el" href="classuart__wishbone__slave.html"><Entity uart_wishbone_slave> </a></em></td></tr>
<tr class="memdesc:abc849ae7612bb6c8206d5bb023aee9b7"><td class="mdescLeft"> </td><td class="mdescRight">Reset Input. <a href="#abc849ae7612bb6c8206d5bb023aee9b7"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="Signals"></a>
Signals</h2></td></tr>
<tr class="memitem:acef6c685139cf878735d133cbb1c3f39"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acef6c685139cf878735d133cbb1c3f39"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#acef6c685139cf878735d133cbb1c3f39">CLK</a>  </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memitem:a1b2ce329025fb7093ff70e636d12a866"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1b2ce329025fb7093ff70e636d12a866"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a1b2ce329025fb7093ff70e636d12a866">RST</a>  </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memitem:a390d1a631f1b4e3a4e6c8100a89d2a1a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a390d1a631f1b4e3a4e6c8100a89d2a1a"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a390d1a631f1b4e3a4e6c8100a89d2a1a">ACK</a>  </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memitem:ac80819cc19e23b048a63969ff1734fe3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac80819cc19e23b048a63969ff1734fe3"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#ac80819cc19e23b048a63969ff1734fe3">WE</a>  </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memitem:abdf56a973f6d5e4f89aaeda24c14daae"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abdf56a973f6d5e4f89aaeda24c14daae"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#abdf56a973f6d5e4f89aaeda24c14daae">STB</a>  </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memitem:abadff3227c7c9a2efb08edb0c8ad8748"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abadff3227c7c9a2efb08edb0c8ad8748"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#abadff3227c7c9a2efb08edb0c8ad8748">ADR</a>  </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">1</span> <span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memitem:aed15a1c21fea27515d3bb53207f39a32"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aed15a1c21fea27515d3bb53207f39a32"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#aed15a1c21fea27515d3bb53207f39a32">dataI</a>  </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">31</span> <span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memitem:aa0fa98bb667fa3676c31b4542a34b28a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa0fa98bb667fa3676c31b4542a34b28a"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#aa0fa98bb667fa3676c31b4542a34b28a">dataO</a>  </td><td class="memItemRight" valign="bottom"><b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">31</span> <span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr><td colspan="2"><h2><a name="Instantiations"></a>
Instantiations</h2></td></tr>
<tr class="memitem:addc89a1043fac3e419f545918b00304b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="addc89a1043fac3e419f545918b00304b"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#addc89a1043fac3e419f545918b00304b">uSysCon</a> </td><td class="memItemRight" valign="bottom"> <b>SYC0001a</b> <em><a class="el" href="class_s_y_c0001a.html"><Entity SYC0001a></a></em></td></tr>
<tr class="memdesc:addc89a1043fac3e419f545918b00304b"><td class="mdescLeft"> </td><td class="mdescRight">Instantiate <a class="el" href="class_s_y_c0001a.html">SYC0001a</a>. <br/></td></tr>
<tr class="memitem:a17d29dc89d37b4f2942037816f9095f9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a17d29dc89d37b4f2942037816f9095f9"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a17d29dc89d37b4f2942037816f9095f9">uMasterSerial</a> </td><td class="memItemRight" valign="bottom"> <b>SERIALMASTER</b> <em><a class="el" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html"><Entity SERIALMASTER></a></em></td></tr>
<tr class="memdesc:a17d29dc89d37b4f2942037816f9095f9"><td class="mdescLeft"> </td><td class="mdescRight">Instantiate <a class="el" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html">SERIALMASTER</a>. <br/></td></tr>
<tr class="memitem:a869bee07e49a71e28b889f35f114c40f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a869bee07e49a71e28b889f35f114c40f"></a>
<a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a869bee07e49a71e28b889f35f114c40f">uUartWishboneSlave</a> </td><td class="memItemRight" valign="bottom"> <b>uart_wishbone_slave</b> <em><a class="el" href="classuart__wishbone__slave.html"><Entity uart_wishbone_slave></a></em></td></tr>
<tr class="memdesc:a869bee07e49a71e28b889f35f114c40f"><td class="mdescLeft"> </td><td class="mdescRight">Instantiate <a class="el" href="classuart__wishbone__slave.html">uart_wishbone_slave</a>. <br/></td></tr>
</table>
<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
<div class="textblock"><p>Declaring the components (<a class="el" href="class_s_y_c0001a.html">SYC0001a</a>, <a class="el" href="class_s_e_r_i_a_l_m_a_s_t_e_r.html">SERIALMASTER</a>, <a class="el" href="classuart__wishbone__slave.html">uart_wishbone_slave</a>) </p>
<p>Just instantiate and connect the various components </p>
<p>Definition at line <a class="el" href="_i_n_t_e_r_c_o_n___p2_p_8vhd_source.html#l00022">22</a> of file <a class="el" href="_i_n_t_e_r_c_o_n___p2_p_8vhd_source.html">INTERCON_P2P.vhd</a>.</p>
</div><hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a99b85cc71dbbaa06e16f4d4351530462"></a>
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<td class="memname"><a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a99b85cc71dbbaa06e16f4d4351530462">SYC0001a</a> <b><span class="vhdlchar"> </span></b> <code> [Component]</code></td>
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<p>Clock output. </p>
<p>Reset output Clock input Reset input </p>
<p>Definition at line <a class="el" href="_i_n_t_e_r_c_o_n___p2_p_8vhd_source.html#l00023">23</a> of file <a class="el" href="_i_n_t_e_r_c_o_n___p2_p_8vhd_source.html">INTERCON_P2P.vhd</a>.</p>
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<a class="anchor" id="a3eba7772cc5be92821da2ebda4b73fae"></a>
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<td class="memname"><a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#a3eba7772cc5be92821da2ebda4b73fae">SERIALMASTER</a> <b><span class="vhdlchar"> </span></b> <code> [Component]</code></td>
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<p>Ack input. </p>
<p>Address output Clock input Cycle output Data input Data output Reset input Select output Strobe output (Works like a chip select) Write enable Signal byte received (Used to debug on the out leds) </p>
<p>Definition at line <a class="el" href="_i_n_t_e_r_c_o_n___p2_p_8vhd_source.html#l00034">34</a> of file <a class="el" href="_i_n_t_e_r_c_o_n___p2_p_8vhd_source.html">INTERCON_P2P.vhd</a>.</p>
</div>
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<a class="anchor" id="abc849ae7612bb6c8206d5bb023aee9b7"></a>
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<td class="memname"><a class="el" href="class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral.html#abc849ae7612bb6c8206d5bb023aee9b7">uart_wishbone_slave</a> <b><span class="vhdlchar"> </span></b> <code> [Component]</code></td>
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<p>Reset Input. </p>
<p>Clock Input Address input Data Input 0 Data Output 0 Write enable input Strobe input (Works like a chip select) Ack output Uart serial input Flag to indicate data avaible Uart serial output </p>
<p>Definition at line <a class="el" href="_i_n_t_e_r_c_o_n___p2_p_8vhd_source.html#l00053">53</a> of file <a class="el" href="_i_n_t_e_r_c_o_n___p2_p_8vhd_source.html">INTERCON_P2P.vhd</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
<li>E:/uart_block/hdl/iseProject/<a class="el" href="_i_n_t_e_r_c_o_n___p2_p_8vhd_source.html">INTERCON_P2P.vhd</a></li>
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