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<a href="#Ports">Ports</a> |
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Inheritance diagram for uart_control:</div>
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Entities</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top"><a class="el" href="classuart__control_1_1_behavioral.html">Behavioral</a>  </td><td class="memItemRight" valign="bottom">architecture</td></tr>
<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Uart control unit. <a href="classuart__control_1_1_behavioral.html#details">More...</a><br/></td></tr>
<br/>
<br/>
<tr><td colspan="2"><h2><a name="Use Clauses"></a>
Use Clauses</h2></td></tr>
<tr class="memitem:ac442dca664056131bdaf5c92e4351e01"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac442dca664056131bdaf5c92e4351e01"></a>
<a class="el" href="classuart__control.html#ac442dca664056131bdaf5c92e4351e01">pkgDefinitions</a> </td><td class="memItemRight" valign="bottom"> <b>Package</b><em><a class="el" href="classpkg_definitions.html"> <pkgDefinitions></a></td></tr>
<tr class="memdesc:ac442dca664056131bdaf5c92e4351e01"><td class="mdescLeft"> </td><td class="mdescRight">Use CPU Definitions package. <br/></td></tr>
<tr><td colspan="2"><h2><a name="Ports"></a>
Ports</h2></td></tr>
<tr class="memitem:a9d3a5df2e98b99b950613d125404f7e7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9d3a5df2e98b99b950613d125404f7e7"></a>
<a class="el" href="classuart__control.html#a9d3a5df2e98b99b950613d125404f7e7">rst</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a9d3a5df2e98b99b950613d125404f7e7"><td class="mdescLeft"> </td><td class="mdescRight">Global reset. <br/></td></tr>
<tr class="memitem:aaa012193baea07aae07ac241afc38d4e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aaa012193baea07aae07ac241afc38d4e"></a>
<a class="el" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e">clk</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:aaa012193baea07aae07ac241afc38d4e"><td class="mdescLeft"> </td><td class="mdescRight">Global clock. <br/></td></tr>
<tr class="memitem:a5d0f1fd17d4ada84491cbbcdff7bd59c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5d0f1fd17d4ada84491cbbcdff7bd59c"></a>
<a class="el" href="classuart__control.html#a5d0f1fd17d4ada84491cbbcdff7bd59c">WE</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a5d0f1fd17d4ada84491cbbcdff7bd59c"><td class="mdescLeft"> </td><td class="mdescRight">Write enable. <br/></td></tr>
<tr class="memitem:a26488fd3af03df7e52e89685254581d9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a26488fd3af03df7e52e89685254581d9"></a>
<a class="el" href="classuart__control.html#a26488fd3af03df7e52e89685254581d9">reg_addr</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">1</span> <span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a26488fd3af03df7e52e89685254581d9"><td class="mdescLeft"> </td><td class="mdescRight">Register address. <br/></td></tr>
<tr class="memitem:ae66e1f3b5a7b302a165fd87d2ebf8008"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae66e1f3b5a7b302a165fd87d2ebf8008"></a>
<a class="el" href="classuart__control.html#ae66e1f3b5a7b302a165fd87d2ebf8008">start</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:ae66e1f3b5a7b302a165fd87d2ebf8008"><td class="mdescLeft"> </td><td class="mdescRight">Start (Strobe) <br/></td></tr>
<tr class="memitem:a4772fc34e10751f941e00c7f532d3a51"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4772fc34e10751f941e00c7f532d3a51"></a>
<a class="el" href="classuart__control.html#a4772fc34e10751f941e00c7f532d3a51">done</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">out</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a4772fc34e10751f941e00c7f532d3a51"><td class="mdescLeft"> </td><td class="mdescRight">Done (ACK) <br/></td></tr>
<tr class="memitem:a6a4e14f575e5b97e6af7829108a9cdb6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6a4e14f575e5b97e6af7829108a9cdb6"></a>
<a class="el" href="classuart__control.html#a6a4e14f575e5b97e6af7829108a9cdb6">DAT_I</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar"> </span><span class="vhdlchar">-</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">1</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a6a4e14f575e5b97e6af7829108a9cdb6"><td class="mdescLeft"> </td><td class="mdescRight">Data Input (Wishbone) <br/></td></tr>
<tr class="memitem:aa0441f210e0ee245a9ee654ee0ecb105"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa0441f210e0ee245a9ee654ee0ecb105"></a>
<a class="el" href="classuart__control.html#aa0441f210e0ee245a9ee654ee0ecb105">DAT_O</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">out</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar"> </span><span class="vhdlchar">-</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">1</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:aa0441f210e0ee245a9ee654ee0ecb105"><td class="mdescLeft"> </td><td class="mdescRight">Data output (Wishbone) <br/></td></tr>
<tr class="memitem:ad78e0a527c5f5c8c3ffa83c438b6f61f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad78e0a527c5f5c8c3ffa83c438b6f61f"></a>
<a class="el" href="classuart__control.html#ad78e0a527c5f5c8c3ffa83c438b6f61f">baud_wait</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">out</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar"> </span><span class="vhdlchar">-</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">1</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:ad78e0a527c5f5c8c3ffa83c438b6f61f"><td class="mdescLeft"> </td><td class="mdescRight">Signal to control the baud rate frequency. <br/></td></tr>
<tr class="memitem:af5fbd616289aa28ef674937c72548374"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af5fbd616289aa28ef674937c72548374"></a>
<a class="el" href="classuart__control.html#af5fbd616289aa28ef674937c72548374">data_byte_tx</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">out</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">nBits</span><span class="vhdlchar"> </span><span class="vhdlchar">-</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">1</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:af5fbd616289aa28ef674937c72548374"><td class="mdescLeft"> </td><td class="mdescRight">1 Byte to be send to <a class="el" href="classserial__transmitter.html">serial_transmitter</a> <br/></td></tr>
<tr class="memitem:a938ea181dcf736513f3743dcf22dbf85"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a938ea181dcf736513f3743dcf22dbf85"></a>
<a class="el" href="classuart__control.html#a938ea181dcf736513f3743dcf22dbf85">data_byte_rx</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic_vector</span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar">(</span><span class="vhdlchar"> </span><span class="vhdlchar">nBits</span><span class="vhdlchar"> </span><span class="vhdlchar">-</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">1</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlkeyword">downto</span><span class="vhdlchar"> </span><span class="vhdlchar"> </span><span class="vhdlchar"> </span> <span class="vhdldigit">0</span> <span class="vhdlchar"> </span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a938ea181dcf736513f3743dcf22dbf85"><td class="mdescLeft"> </td><td class="mdescRight">1 Byte to be received by <a class="el" href="classserial__receiver.html">serial_receiver</a> <br/></td></tr>
<tr class="memitem:af90e032a76aef85021ee288bbec12e11"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af90e032a76aef85021ee288bbec12e11"></a>
<a class="el" href="classuart__control.html#af90e032a76aef85021ee288bbec12e11">tx_data_sent</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:af90e032a76aef85021ee288bbec12e11"><td class="mdescLeft"> </td><td class="mdescRight">Signal comming from <a class="el" href="classserial__transmitter.html">serial_transmitter</a>. <br/></td></tr>
<tr class="memitem:ac8df6578912d098bdb9f21cb0509fb63"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac8df6578912d098bdb9f21cb0509fb63"></a>
<a class="el" href="classuart__control.html#ac8df6578912d098bdb9f21cb0509fb63">tx_start</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">out</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:ac8df6578912d098bdb9f21cb0509fb63"><td class="mdescLeft"> </td><td class="mdescRight">Signal to start sending serial data... <br/></td></tr>
<tr class="memitem:a665e6854e6570b00bd7d35db2049f54f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a665e6854e6570b00bd7d35db2049f54f"></a>
<a class="el" href="classuart__control.html#a665e6854e6570b00bd7d35db2049f54f">rst_comm_blocks</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">out</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a665e6854e6570b00bd7d35db2049f54f"><td class="mdescLeft"> </td><td class="mdescRight">Reset Communication blocks. <br/></td></tr>
<tr class="memitem:a0f38cbc4316d4bba03252027fe0fabc7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0f38cbc4316d4bba03252027fe0fabc7"></a>
<a class="el" href="classuart__control.html#a0f38cbc4316d4bba03252027fe0fabc7">rx_data_ready</a>  </td><td class="memItemRight" valign="bottom"> <b><b><span class="vhdlkeyword">in</span><span class="vhdlchar"> </span></b></b> <b><span class="comment">std_logic</span><span class="vhdlchar"> </span></b></td></tr>
<tr class="memdesc:a0f38cbc4316d4bba03252027fe0fabc7"><td class="mdescLeft"> </td><td class="mdescRight">Signal comming from <a class="el" href="classserial__receiver.html">serial_receiver</a>. <br/></td></tr>
</table>
<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
<div class="textblock">
<p>Definition at line <a class="el" href="uart__control_8vhd_source.html#l00011">11</a> of file <a class="el" href="uart__control_8vhd_source.html">uart_control.vhd</a>.</p>
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