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<a href="test_divisor_8vhd.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001
<a name="l00003"></a>00003
<a name="l00005"></a>00005 <span class="vhdlkeyword">library </span><span class="keywordflow">IEEE</span>;
<a name="l00006"></a>00006 <span class="vhdlkeyword">use </span>IEEE.STD_LOGIC_1164.<span class="vhdlkeyword">ALL</span>;
<a name="l00007"></a>00007 <span class="vhdlkeyword">use </span>IEEE.std_logic_arith.<span class="vhdlkeyword">all</span>;
<a name="l00008"></a>00008
<a name="l00010"></a><a class="code" href="classtest_divisor.html#ac442dca664056131bdaf5c92e4351e01">00010</a> <span class="vhdlkeyword">use </span>work.pkgDefinitions.<span class="vhdlkeyword">all</span>;
<a name="l00011"></a>00011
<a name="l00012"></a><a class="code" href="classtest_divisor.html">00012</a> <span class="keywordflow">ENTITY </span><a class="code" href="classtest_divisor.html">testDivisor</a> <span class="vhdlkeyword">IS</span>
<a name="l00013"></a>00013 <span class="vhdlkeyword">END</span> <span class="vhdlchar">testDivisor</span>;
<a name="l00014"></a>00014
<a name="l00017"></a><a class="code" href="classtest_divisor_1_1behavior.html">00017</a> <span class="vhdlkeyword">ARCHITECTURE</span> behavior <span class="vhdlkeyword">OF</span> <a class="code" href="classtest_divisor.html">testDivisor</a> IS
<a name="l00018"></a>00018 <span class="keyword"></span>
<a name="l00019"></a>00019 <span class="keyword"> -- <span class="vhdlkeyword">Component</span> Declaration <span class="vhdlkeyword">for</span> the Unit Under Test (UUT)</span>
<a name="l00020"></a>00020
<a name="l00021"></a><a class="code" href="classtest_divisor_1_1behavior.html#ab31bbf4e04b601f06da44e54e616cc99">00021</a> <span class="vhdlkeyword">COMPONENT</span> <a class="code" href="classdivisor.html">divisor</a>
<a name="l00022"></a>00022 <span class="vhdlkeyword">Port</span> ( <a class="code" href="classdivisor.html#a0ddd7f10f240eabbaa5f593dc724676d" title="Reset input.">rst</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00023"></a>00023 <a class="code" href="classdivisor.html#afccc0679a700cd9acf53b87c41fee67a" title="Clock input.">clk</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00024"></a>00024 <a class="code" href="classdivisor.html#a72b864bee7e5df9aaa6663e15717ee2a" title="Division result (32 bits)">quotient</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00025"></a>00025 <a class="code" href="classdivisor.html#a2e2b27233f56bb5217044913043942fa" title="Reminder result (32 bits)">reminder</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00026"></a>00026 <a class="code" href="classdivisor.html#ad29d3fb6c6ea697db492c43d4a3630eb" title="Numerator (32 bits)">numerator</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00027"></a>00027 <a class="code" href="classdivisor.html#a125151d21c7a62bc99907ddc72a7ebb1" title=""Divide by" number (32 bits)">divident</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00028"></a>00028 done : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC</span>);
<a name="l00029"></a>00029 <span class="vhdlkeyword">END</span> <span class="vhdlkeyword">COMPONENT</span>;
<a name="l00030"></a>00030
<a name="l00031"></a>00031 <span class="keyword"></span>
<a name="l00032"></a>00032 <span class="keyword"> --Inputs</span>
<a name="l00033"></a><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be">00033</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00034"></a><a class="code" href="classtest_divisor_1_1behavior.html#ad8d4742a7eb2e3d3a95e8c0c37d14ed2">00034</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ad8d4742a7eb2e3d3a95e8c0c37d14ed2" title="Signal to connect with UUT.">clk</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00035"></a><a class="code" href="classtest_divisor_1_1behavior.html#ab6d0f470182dc53c3c65afad4c78bddd">00035</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ab6d0f470182dc53c3c65afad4c78bddd" title="Signal to connect with UUT.">numerator</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00036"></a><a class="code" href="classtest_divisor_1_1behavior.html#a45d3fd79b3d4a9c68e45d5bfd00d1fc7">00036</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a45d3fd79b3d4a9c68e45d5bfd00d1fc7" title="Signal to connect with UUT.">divident</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00037"></a>00037 <span class="keyword"></span>
<a name="l00038"></a>00038 <span class="keyword"> --Outputs</span>
<a name="l00039"></a><a class="code" href="classtest_divisor_1_1behavior.html#a0a9f54386a9ef858f70c32ccceb1ab0e">00039</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a0a9f54386a9ef858f70c32ccceb1ab0e" title="Signal to connect with UUT.">quotient</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00040"></a><a class="code" href="classtest_divisor_1_1behavior.html#a4192e4decb5e0fff313ed7578a1fe6a5">00040</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a4192e4decb5e0fff313ed7578a1fe6a5" title="Signal to connect with UUT.">reminder</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00041"></a>00041 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">done</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00042"></a>00042 <span class="keyword"></span>
<a name="l00043"></a>00043 <span class="keyword"> -- Clock period definitions</span>
<a name="l00044"></a>00044 <span class="vhdlkeyword">constant</span> <span class="vhdlchar">clk_period</span> <span class="vhdlchar">:</span> <span class="comment">time</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">10</span> <span class="vhdlchar">ns</span>;
<a name="l00045"></a>00045
<a name="l00046"></a>00046 <span class="vhdlkeyword">BEGIN</span>
<a name="l00047"></a>00047
<a name="l00049"></a>00049 <a class="code" href="dummy.html#a1619316ad715601eb5d3559db829ac05" title="Instantiate the Unit Under Test (UUT)">uut</a>: <a class="code" href="classdivisor.html">divisor</a> <span class="vhdlkeyword">PORT</span> <span class="vhdlkeyword">MAP</span> (
<a name="l00050"></a>00050 <a class="code" href="classdivisor.html#a0ddd7f10f240eabbaa5f593dc724676d" title="Reset input.">rst</a> => <a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a>,
<a name="l00051"></a>00051 <a class="code" href="classdivisor.html#afccc0679a700cd9acf53b87c41fee67a" title="Clock input.">clk</a> => <a class="code" href="classtest_divisor_1_1behavior.html#ad8d4742a7eb2e3d3a95e8c0c37d14ed2" title="Signal to connect with UUT.">clk</a>,
<a name="l00052"></a>00052 <a class="code" href="classdivisor.html#a72b864bee7e5df9aaa6663e15717ee2a" title="Division result (32 bits)">quotient</a> => <a class="code" href="classtest_divisor_1_1behavior.html#a0a9f54386a9ef858f70c32ccceb1ab0e" title="Signal to connect with UUT.">quotient</a>,
<a name="l00053"></a>00053 <a class="code" href="classdivisor.html#a2e2b27233f56bb5217044913043942fa" title="Reminder result (32 bits)">reminder</a> => <a class="code" href="classtest_divisor_1_1behavior.html#a4192e4decb5e0fff313ed7578a1fe6a5" title="Signal to connect with UUT.">reminder</a>,
<a name="l00054"></a>00054 <a class="code" href="classdivisor.html#ad29d3fb6c6ea697db492c43d4a3630eb" title="Numerator (32 bits)">numerator</a> => <a class="code" href="classtest_divisor_1_1behavior.html#ab6d0f470182dc53c3c65afad4c78bddd" title="Signal to connect with UUT.">numerator</a>,
<a name="l00055"></a>00055 <a class="code" href="classdivisor.html#a125151d21c7a62bc99907ddc72a7ebb1" title=""Divide by" number (32 bits)">divident</a> => <a class="code" href="classtest_divisor_1_1behavior.html#a45d3fd79b3d4a9c68e45d5bfd00d1fc7" title="Signal to connect with UUT.">divident</a>,
<a name="l00056"></a>00056 done => done
<a name="l00057"></a>00057 <span class="vhdlchar">)</span>;
<a name="l00058"></a>00058 <span class="keyword"></span>
<a name="l00059"></a>00059 <span class="keyword"> -- Clock <span class="vhdlkeyword">process</span> definitions</span>
<a name="l00060"></a>00060 clk_process :<span class="vhdlkeyword">process</span>
<a name="l00061"></a>00061 <span class="vhdlkeyword">begin</span>
<a name="l00062"></a>00062 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ad8d4742a7eb2e3d3a95e8c0c37d14ed2" title="Signal to connect with UUT.">clk</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00063"></a>00063 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span><span class="vhdlchar">/</span><span class="vhdllogic"></span><span class="vhdllogic">2</span>;
<a name="l00064"></a>00064 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ad8d4742a7eb2e3d3a95e8c0c37d14ed2" title="Signal to connect with UUT.">clk</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00065"></a>00065 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span><span class="vhdlchar">/</span><span class="vhdllogic"></span><span class="vhdllogic">2</span>;
<a name="l00066"></a>00066 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00067"></a>00067
<a name="l00068"></a>00068 <span class="keyword"></span>
<a name="l00069"></a>00069 <span class="keyword"> -- Stimulus <span class="vhdlkeyword">process</span></span>
<a name="l00070"></a>00070 stim_proc: <span class="vhdlkeyword">process</span>
<a name="l00071"></a>00071 <span class="vhdlkeyword">begin</span> <span class="keyword"></span>
<a name="l00072"></a>00072 <span class="keyword"> -- hold reset state <span class="vhdlkeyword">for</span> </span><span class="vhdllogic">100</span> ns.
<a name="l00073"></a>00073 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00074"></a>00074 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ab6d0f470182dc53c3c65afad4c78bddd" title="Signal to connect with UUT.">numerator</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">50000000</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span>;
<a name="l00075"></a>00075 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a45d3fd79b3d4a9c68e45d5bfd00d1fc7" title="Signal to connect with UUT.">divident</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">115200</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span>;
<a name="l00076"></a>00076 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span>;
<a name="l00077"></a>00077 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00078"></a>00078
<a name="l00079"></a>00079 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">until</span> <span class="vhdlchar">done</span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00080"></a>00080 <span class="vhdlkeyword">assert</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a0a9f54386a9ef858f70c32ccceb1ab0e" title="Signal to connect with UUT.">quotient</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">434</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">report</span> <span class="keyword">"Wrong result... expected 434."</span> <span class="vhdlkeyword">severity</span> <span class="vhdlchar">failure</span>;
<a name="l00081"></a>00081 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span>;
<a name="l00082"></a>00082
<a name="l00083"></a>00083 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00084"></a>00084 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#ab6d0f470182dc53c3c65afad4c78bddd" title="Signal to connect with UUT.">numerator</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">40</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span>;
<a name="l00085"></a>00085 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a45d3fd79b3d4a9c68e45d5bfd00d1fc7" title="Signal to connect with UUT.">divident</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">5</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span>;
<a name="l00086"></a>00086 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span>;
<a name="l00087"></a>00087 <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a513fa2f18065f5d31a856b5a7268e6be" title="Signal to connect with UUT.">rst</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00088"></a>00088
<a name="l00089"></a>00089 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">until</span> <span class="vhdlchar">done</span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00090"></a>00090 <span class="vhdlkeyword">assert</span> <span class="vhdlchar"><a class="code" href="classtest_divisor_1_1behavior.html#a0a9f54386a9ef858f70c32ccceb1ab0e" title="Signal to connect with UUT.">quotient</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">8</span><span class="vhdlchar">,</span> <span class="vhdllogic"></span><span class="vhdllogic">32</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">report</span> <span class="keyword">"Wrong result... expected 8."</span> <span class="vhdlkeyword">severity</span> <span class="vhdlchar">failure</span>;
<a name="l00091"></a>00091 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">clk_period</span>;
<a name="l00092"></a>00092 <span class="keyword"></span>
<a name="l00093"></a>00093 <span class="keyword"> -- insert stimulus here </span>
<a name="l00094"></a>00094 <span class="vhdlkeyword">assert</span> <span class="vhdlchar">false</span> <span class="vhdlkeyword">report</span> <span class="keyword">"NONE. End of simulation."</span> <span class="vhdlkeyword">severity</span> <span class="vhdlchar">failure</span>;
<a name="l00095"></a>00095
<a name="l00096"></a>00096 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00097"></a>00097
<a name="l00098"></a>00098 <span class="vhdlkeyword">END</span>;
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