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<div class="fragment"><pre class="fragment"><a name="l00001"></a>00001
<a name="l00002"></a>00002 <span class="vhdlkeyword">LIBRARY </span><span class="keywordflow">ieee</span>;
<a name="l00003"></a>00003 <span class="vhdlkeyword">USE </span>ieee.std_logic_1164.<span class="vhdlkeyword">ALL</span>;
<a name="l00004"></a>00004 <span class="vhdlkeyword">use </span>ieee.std_logic_unsigned.<span class="vhdlkeyword">all</span>;
<a name="l00005"></a>00005 <span class="vhdlkeyword">use </span>ieee.std_logic_arith.<span class="vhdlkeyword">all</span>;
<a name="l00006"></a>00006
<a name="l00008"></a><a class="code" href="classtest_uart__wishbone__slave.html#ac442dca664056131bdaf5c92e4351e01">00008</a> <span class="vhdlkeyword">use </span>work.pkgDefinitions.<span class="vhdlkeyword">all</span>;
<a name="l00009"></a>00009
<a name="l00010"></a><a class="code" href="classtest_uart__wishbone__slave.html">00010</a> <span class="keywordflow">ENTITY </span><a class="code" href="classtest_uart__wishbone__slave.html">testUart_wishbone_slave</a> <span class="vhdlkeyword">IS</span>
<a name="l00011"></a>00011 <span class="vhdlkeyword">END</span> <span class="vhdlchar">testUart_wishbone_slave</span>;
<a name="l00012"></a>00012
<a name="l00013"></a><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html">00013</a> <span class="vhdlkeyword">ARCHITECTURE</span> behavior <span class="vhdlkeyword">OF</span> <a class="code" href="classtest_uart__wishbone__slave.html">testUart_wishbone_slave</a> IS
<a name="l00014"></a>00014 <span class="keyword"></span>
<a name="l00015"></a>00015 <span class="keyword"> -- <span class="vhdlkeyword">Component</span> Declaration <span class="vhdlkeyword">for</span> the Unit Under Test (UUT)</span>
<a name="l00016"></a>00016
<a name="l00017"></a><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a5c22d67786c8d4257bb37aa2efb6f261">00017</a> <span class="vhdlkeyword">COMPONENT</span> <a class="code" href="classuart__wishbone__slave.html">uart_wishbone_slave</a>
<a name="l00018"></a>00018 <span class="vhdlkeyword">Port</span> ( <a class="code" href="classuart__wishbone__slave.html#a4775682dc01dcbf48f20a731490ff2da" title="Reset Input.">RST_I</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00019"></a>00019 <a class="code" href="classuart__wishbone__slave.html#aa26da3641303aaf250c88cbdf3d8a1a3" title="Clock Input.">CLK_I</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00020"></a>00020 <a class="code" href="classuart__wishbone__slave.html#aca7516cbd7b6a93eac24e720fc01760c" title="Address input.">ADR_I0</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> (<span class="vhdllogic"></span><span class="vhdllogic">1</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00021"></a>00021 <a class="code" href="classuart__wishbone__slave.html#ad423901fb91ee750587d52bd9ddb2001" title="Data Input 0.">DAT_I0</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> (<span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00022"></a>00022 <a class="code" href="classuart__wishbone__slave.html#a5779ba7b1bb275d5e56907020420ca27" title="Data Output 0.">DAT_O0</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC_VECTOR</span> (<span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00023"></a>00023 <a class="code" href="classuart__wishbone__slave.html#a32a749c5f0d113303c3de1fa917b8f56" title="Write enable input.">WE_I</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00024"></a>00024 <a class="code" href="classuart__wishbone__slave.html#af3bb8cfb2912c0d4ce792bd6c53d6a4c" title="Strobe input (Works like a chip select)">STB_I</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00025"></a>00025 <a class="code" href="classuart__wishbone__slave.html#aeec8b0022ebb92b40f746bf13cf7319c" title="Ack output.">ACK_O</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC</span>;
<a name="l00026"></a>00026 <span class="keyword"></span>
<a name="l00027"></a>00027 <span class="keyword"> -- NON-WISHBONE Signals</span>
<a name="l00028"></a>00028 <a class="code" href="classuart__wishbone__slave.html#aafe347fe5fc89efa63d92386f60c5f50" title="Uart serial input.">serial_in</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00029"></a>00029 <a class="code" href="classuart__wishbone__slave.html#ad55ceaa2b85f0ff8d37ba499fc620a61" title="Flag to indicate data avaible.">data_Avaible</a> : <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00030"></a>00030 serial_out : <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>
<a name="l00031"></a>00031 );
<a name="l00032"></a>00032 <span class="vhdlkeyword">END</span> <span class="vhdlkeyword">COMPONENT</span>;
<a name="l00033"></a>00033
<a name="l00034"></a>00034 <span class="keyword"></span>
<a name="l00035"></a>00035 <span class="keyword"> --Inputs</span>
<a name="l00036"></a><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a6ee791bdb5df4ccca9dd8a946696dd8a">00036</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a6ee791bdb5df4ccca9dd8a946696dd8a" title="Signal to connect with UUT.">RST_I</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00037"></a><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4c7b3772ac2a67a7c972f606d2cc4ec7">00037</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4c7b3772ac2a67a7c972f606d2cc4ec7" title="Signal to connect with UUT.">CLK_I</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00038"></a><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae">00038</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">1</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00039"></a><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4b087814632daf135cbc38c252bbaf77">00039</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4b087814632daf135cbc38c252bbaf77" title="Signal to connect with UUT.">DAT_I0</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00040"></a>00040 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">WE_I</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00041"></a>00041 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">STB_I</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00042"></a>00042 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">serial_in</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span> <span class="vhdlchar">:=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00043"></a>00043 <span class="keyword"></span>
<a name="l00044"></a>00044 <span class="keyword"> --Outputs</span>
<a name="l00045"></a><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#aa444d95093cb5f8197bb92d21da1f43a">00045</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#aa444d95093cb5f8197bb92d21da1f43a" title="Signal to connect with UUT.">DAT_O0</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00046"></a><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a21f50c72e4e45c54ea44e014934312d4">00046</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a21f50c72e4e45c54ea44e014934312d4" title="Signal to connect with UUT.">ACK_O</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00047"></a><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a30dda061cfa67e7c4d84ec0f5d1cb295">00047</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a30dda061cfa67e7c4d84ec0f5d1cb295" title="Signal to connect with UUT.">serial_out</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00048"></a><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a051f773441045ed070bde8d6139dd817">00048</a> <span class="vhdlkeyword">signal</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a051f773441045ed070bde8d6139dd817" title="Signal to connect with UUT.">data_Avaible</a></span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00049"></a>00049 <span class="keyword"></span>
<a name="l00050"></a>00050 <span class="keyword"> -- Clock period definitions (</span><span class="vhdllogic">1</span>.8432MHz)
<a name="l00051"></a>00051 <span class="vhdlkeyword">constant</span> <span class="vhdlchar">CLK_I_period</span> <span class="vhdlchar">:</span> <span class="comment">time</span> <span class="vhdlchar">:=</span> <span class="vhdllogic"></span><span class="vhdllogic">20</span> <span class="vhdlchar">ns</span>;<span class="keyword"> -- </span><span class="vhdllogic">0</span>.543us (<span class="vhdllogic">1</span>.8432Mhz) 2ns (50Mhz)
<a name="l00052"></a>00052
<a name="l00053"></a>00053 <span class="vhdlkeyword">BEGIN</span>
<a name="l00054"></a>00054
<a name="l00056"></a>00056 uut: <a class="code" href="classuart__wishbone__slave.html">uart_wishbone_slave</a> <span class="vhdlkeyword">PORT</span> <span class="vhdlkeyword">MAP</span> (
<a name="l00057"></a>00057 <a class="code" href="classuart__wishbone__slave.html#a4775682dc01dcbf48f20a731490ff2da" title="Reset Input.">RST_I</a> => <a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a6ee791bdb5df4ccca9dd8a946696dd8a" title="Signal to connect with UUT.">RST_I</a>,
<a name="l00058"></a>00058 <a class="code" href="classuart__wishbone__slave.html#aa26da3641303aaf250c88cbdf3d8a1a3" title="Clock Input.">CLK_I</a> => <a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4c7b3772ac2a67a7c972f606d2cc4ec7" title="Signal to connect with UUT.">CLK_I</a>,
<a name="l00059"></a>00059 <a class="code" href="classuart__wishbone__slave.html#aca7516cbd7b6a93eac24e720fc01760c" title="Address input.">ADR_I0</a> => <a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a>,
<a name="l00060"></a>00060 <a class="code" href="classuart__wishbone__slave.html#ad423901fb91ee750587d52bd9ddb2001" title="Data Input 0.">DAT_I0</a> => <a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4b087814632daf135cbc38c252bbaf77" title="Signal to connect with UUT.">DAT_I0</a>,
<a name="l00061"></a>00061 <a class="code" href="classuart__wishbone__slave.html#a5779ba7b1bb275d5e56907020420ca27" title="Data Output 0.">DAT_O0</a> => <a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#aa444d95093cb5f8197bb92d21da1f43a" title="Signal to connect with UUT.">DAT_O0</a>,
<a name="l00062"></a>00062 <a class="code" href="classuart__wishbone__slave.html#a32a749c5f0d113303c3de1fa917b8f56" title="Write enable input.">WE_I</a> => WE_I,
<a name="l00063"></a>00063 <a class="code" href="classuart__wishbone__slave.html#af3bb8cfb2912c0d4ce792bd6c53d6a4c" title="Strobe input (Works like a chip select)">STB_I</a> => STB_I,
<a name="l00064"></a>00064 <a class="code" href="classuart__wishbone__slave.html#aeec8b0022ebb92b40f746bf13cf7319c" title="Ack output.">ACK_O</a> => <a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a21f50c72e4e45c54ea44e014934312d4" title="Signal to connect with UUT.">ACK_O</a>,
<a name="l00065"></a>00065 <a class="code" href="classuart__wishbone__slave.html#aafe347fe5fc89efa63d92386f60c5f50" title="Uart serial input.">serial_in</a> => serial_in,
<a name="l00066"></a>00066 <a class="code" href="classuart__wishbone__slave.html#ad55ceaa2b85f0ff8d37ba499fc620a61" title="Flag to indicate data avaible.">data_Avaible</a> => <a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a051f773441045ed070bde8d6139dd817" title="Signal to connect with UUT.">data_Avaible</a>,
<a name="l00067"></a>00067 serial_out => <a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a30dda061cfa67e7c4d84ec0f5d1cb295" title="Signal to connect with UUT.">serial_out</a>
<a name="l00068"></a>00068 <span class="vhdlchar">)</span>;
<a name="l00069"></a>00069 <span class="keyword"></span>
<a name="l00070"></a>00070 <span class="keyword"> -- Clock <span class="vhdlkeyword">process</span> definitions</span>
<a name="l00071"></a>00071 CLK_I_process :<span class="vhdlkeyword">process</span>
<a name="l00072"></a>00072 <span class="vhdlkeyword">begin</span>
<a name="l00073"></a>00073 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4c7b3772ac2a67a7c972f606d2cc4ec7" title="Signal to connect with UUT.">CLK_I</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00074"></a>00074 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">CLK_I_period</span><span class="vhdlchar">/</span><span class="vhdllogic"></span><span class="vhdllogic">2</span>;
<a name="l00075"></a>00075 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4c7b3772ac2a67a7c972f606d2cc4ec7" title="Signal to connect with UUT.">CLK_I</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00076"></a>00076 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">CLK_I_period</span><span class="vhdlchar">/</span><span class="vhdllogic"></span><span class="vhdllogic">2</span>;
<a name="l00077"></a>00077 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00078"></a>00078
<a name="l00079"></a>00079 <span class="keyword"></span>
<a name="l00080"></a>00080 <span class="keyword"> -- Stimulus <span class="vhdlkeyword">process</span></span>
<a name="l00081"></a>00081 stim_proc: <span class="vhdlkeyword">process</span>
<a name="l00082"></a>00082 <span class="vhdlkeyword">begin</span> <span class="keyword"></span>
<a name="l00083"></a>00083 <span class="keyword"> -- Reset the slave</span>
<a name="l00084"></a>00084 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a6ee791bdb5df4ccca9dd8a946696dd8a" title="Signal to connect with UUT.">RST_I</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00085"></a>00085 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00086"></a>00086 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">CLK_I_period</span>;
<a name="l00087"></a>00087 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a6ee791bdb5df4ccca9dd8a946696dd8a" title="Signal to connect with UUT.">RST_I</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00088"></a>00088 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">CLK_I_period</span>;
<a name="l00089"></a>00089 <span class="keyword"></span>
<a name="l00090"></a>00090 <span class="keyword"> -- Configure the clock... </span>
<a name="l00091"></a>00091 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"00"</span>;
<a name="l00092"></a>00092 <span class="vhdlchar">WE_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00093"></a>00093 <span class="vhdlchar">STB_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00094"></a>00094 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4b087814632daf135cbc38c252bbaf77" title="Signal to connect with UUT.">DAT_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">50000000</span><span class="vhdlchar">,</span> <span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span>;
<a name="l00095"></a>00095 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">until</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a21f50c72e4e45c54ea44e014934312d4" title="Signal to connect with UUT.">ACK_O</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00096"></a>00096 <span class="vhdlchar">WE_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00097"></a>00097 <span class="vhdlchar">STB_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00098"></a>00098 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdlchar">U</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00099"></a>00099 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">CLK_I_period</span>;
<a name="l00100"></a>00100 <span class="keyword"></span>
<a name="l00101"></a>00101 <span class="keyword"> -- Configure the Baud... </span>
<a name="l00102"></a>00102 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"01"</span>;
<a name="l00103"></a>00103 <span class="vhdlchar">WE_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00104"></a>00104 <span class="vhdlchar">STB_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00105"></a>00105 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4b087814632daf135cbc38c252bbaf77" title="Signal to connect with UUT.">DAT_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">conv_std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">115200</span><span class="vhdlchar">,</span> <span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span>;
<a name="l00106"></a>00106 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">until</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a21f50c72e4e45c54ea44e014934312d4" title="Signal to connect with UUT.">ACK_O</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00107"></a>00107 <span class="vhdlchar">WE_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00108"></a>00108 <span class="vhdlchar">STB_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00109"></a>00109 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdlchar">U</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00110"></a>00110 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">CLK_I_period</span><span class="vhdlchar">*</span><span class="vhdllogic"></span><span class="vhdllogic">40</span>;
<a name="l00111"></a>00111 <span class="keyword"></span>
<a name="l00112"></a>00112 <span class="keyword"> -- Ask <span class="vhdlkeyword">to</span> send some data...(</span><span class="vhdllogic">0xC4</span>)
<a name="l00113"></a>00113 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"10"</span>;
<a name="l00114"></a>00114 <span class="vhdlchar">WE_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00115"></a>00115 <span class="vhdlchar">STB_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00116"></a>00116 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4b087814632daf135cbc38c252bbaf77" title="Signal to connect with UUT.">DAT_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">x</span><span class="vhdllogic">"000000C4"</span>;
<a name="l00117"></a>00117 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">until</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a21f50c72e4e45c54ea44e014934312d4" title="Signal to connect with UUT.">ACK_O</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00118"></a>00118 <span class="vhdlchar">WE_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00119"></a>00119 <span class="vhdlchar">STB_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00120"></a>00120 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdlchar">U</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00121"></a>00121 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">CLK_I_period</span><span class="vhdlchar">*</span><span class="vhdllogic"></span><span class="vhdllogic">5000</span>;
<a name="l00122"></a>00122 <span class="keyword"></span>
<a name="l00123"></a>00123 <span class="keyword"> -- Receive </span><span class="vhdllogic">0x55</span> value (<span class="vhdllogic">01010101</span>)
<a name="l00124"></a>00124 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;<span class="keyword"> -- Start <span class="comment">bit</span></span>
<a name="l00125"></a>00125 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdllogic"></span><span class="vhdllogic">8</span>.<span class="vhdllogic">68</span> <span class="vhdlchar">us</span>;
<a name="l00126"></a>00126
<a name="l00127"></a>00127 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00128"></a>00128 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdllogic"></span><span class="vhdllogic">8</span>.<span class="vhdllogic">68</span> <span class="vhdlchar">us</span>;
<a name="l00129"></a>00129 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00130"></a>00130 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdllogic"></span><span class="vhdllogic">8</span>.<span class="vhdllogic">68</span> <span class="vhdlchar">us</span>;
<a name="l00131"></a>00131 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00132"></a>00132 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdllogic"></span><span class="vhdllogic">8</span>.<span class="vhdllogic">68</span> <span class="vhdlchar">us</span>;
<a name="l00133"></a>00133 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00134"></a>00134 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdllogic"></span><span class="vhdllogic">8</span>.<span class="vhdllogic">68</span> <span class="vhdlchar">us</span>;
<a name="l00135"></a>00135 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00136"></a>00136 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdllogic"></span><span class="vhdllogic">8</span>.<span class="vhdllogic">68</span> <span class="vhdlchar">us</span>;
<a name="l00137"></a>00137 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00138"></a>00138 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdllogic"></span><span class="vhdllogic">8</span>.<span class="vhdllogic">68</span> <span class="vhdlchar">us</span>;
<a name="l00139"></a>00139 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00140"></a>00140 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdllogic"></span><span class="vhdllogic">8</span>.<span class="vhdllogic">68</span> <span class="vhdlchar">us</span>;
<a name="l00141"></a>00141 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00142"></a>00142 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdllogic"></span><span class="vhdllogic">8</span>.<span class="vhdllogic">68</span> <span class="vhdlchar">us</span>;
<a name="l00143"></a>00143 <span class="keyword"></span>
<a name="l00144"></a>00144 <span class="keyword"> -- Stop <span class="comment">bit</span> here</span>
<a name="l00145"></a>00145 <span class="vhdlchar">serial_in</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00146"></a>00146 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">CLK_I_period</span><span class="vhdlchar">*</span><span class="vhdllogic"></span><span class="vhdllogic">5000</span>;
<a name="l00147"></a>00147 <span class="keyword"></span>
<a name="l00148"></a>00148 <span class="keyword"> -- Check content by reading the <span class="vhdlkeyword">register</span> (Should be </span><span class="vhdllogic">0x55</span>)
<a name="l00149"></a>00149 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"11"</span>;
<a name="l00150"></a>00150 <span class="vhdlchar">WE_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00151"></a>00151 <span class="vhdlchar">STB_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00152"></a>00152 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">until</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a21f50c72e4e45c54ea44e014934312d4" title="Signal to connect with UUT.">ACK_O</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00153"></a>00153 <span class="vhdlchar">STB_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00154"></a>00154 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdlchar">U</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00155"></a>00155 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">CLK_I_period</span><span class="vhdlchar">*</span><span class="vhdllogic"></span><span class="vhdllogic">5000</span>;
<a name="l00156"></a>00156 <span class="keyword"></span>
<a name="l00157"></a>00157 <span class="keyword"> -- Ask <span class="vhdlkeyword">to</span> send some data...(</span><span class="vhdllogic">0x55</span>)
<a name="l00158"></a>00158 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdllogic">"10"</span>;
<a name="l00159"></a>00159 <span class="vhdlchar">WE_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00160"></a>00160 <span class="vhdlchar">STB_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00161"></a>00161 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a4b087814632daf135cbc38c252bbaf77" title="Signal to connect with UUT.">DAT_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">x</span><span class="vhdllogic">"00000055"</span>;
<a name="l00162"></a>00162 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">until</span> <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a21f50c72e4e45c54ea44e014934312d4" title="Signal to connect with UUT.">ACK_O</a></span> <span class="vhdlchar">=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">'</span>;
<a name="l00163"></a>00163 <span class="vhdlchar">WE_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00164"></a>00164 <span class="vhdlchar">STB_I</span> <span class="vhdlchar"><=</span> <span class="vhdlchar">'</span><span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">'</span>;
<a name="l00165"></a>00165 <span class="vhdlchar"><a class="code" href="classtest_uart__wishbone__slave_1_1behavior.html#a7a6abb7d1c91a8dfcf6ab3d0bf78a3ae" title="Signal to connect with UUT.">ADR_I0</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">(</span><span class="vhdlkeyword">others</span> <span class="vhdlchar">=</span><span class="vhdlchar">></span> <span class="vhdlchar">'</span><span class="vhdlchar">U</span><span class="vhdlchar">'</span><span class="vhdlchar">)</span>;
<a name="l00166"></a>00166 <span class="vhdlkeyword">wait</span> <span class="vhdlkeyword">for</span> <span class="vhdlchar">CLK_I_period</span><span class="vhdlchar">*</span><span class="vhdllogic"></span><span class="vhdllogic">5000</span>;
<a name="l00167"></a>00167
<a name="l00168"></a>00168
<a name="l00169"></a>00169 <span class="keyword"></span>
<a name="l00170"></a>00170 <span class="keyword"> -- Stop Simulation</span>
<a name="l00171"></a>00171 <span class="vhdlkeyword">assert</span> <span class="vhdlchar">false</span> <span class="vhdlkeyword">report</span> <span class="keyword">"NONE. End of simulation."</span> <span class="vhdlkeyword">severity</span> <span class="vhdlchar">failure</span>;
<a name="l00172"></a>00172 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span>;
<a name="l00173"></a>00173
<a name="l00174"></a>00174 <span class="vhdlkeyword">END</span>;
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