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<a href="uart__wishbone__slave_8vhd.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001
<a name="l00003"></a>00003
<a name="l00004"></a>00004 <span class="vhdlkeyword">library </span><span class="keywordflow">IEEE</span>;
<a name="l00005"></a>00005 <span class="vhdlkeyword">use </span>IEEE.STD_LOGIC_1164.<span class="vhdlkeyword">ALL</span>;
<a name="l00006"></a>00006
<a name="l00008"></a><a class="code" href="classuart__wishbone__slave.html#ac442dca664056131bdaf5c92e4351e01">00008</a> <span class="vhdlkeyword">use </span>work.pkgDefinitions.<span class="vhdlkeyword">all</span>;
<a name="l00009"></a>00009
<a name="l00010"></a><a class="code" href="classuart__wishbone__slave.html">00010</a> <span class="keywordflow">entity </span><a class="code" href="classuart__wishbone__slave.html">uart_wishbone_slave</a> <span class="vhdlkeyword">is</span>
<a name="l00011"></a><a class="code" href="classuart__wishbone__slave.html#a4775682dc01dcbf48f20a731490ff2da">00011</a> <span class="vhdlkeyword">Port</span> <span class="vhdlchar">(</span> <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#a4775682dc01dcbf48f20a731490ff2da" title="Reset Input.">RST_I</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00012"></a><a class="code" href="classuart__wishbone__slave.html#aa26da3641303aaf250c88cbdf3d8a1a3">00012</a> <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#aa26da3641303aaf250c88cbdf3d8a1a3" title="Clock Input.">CLK_I</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00013"></a><a class="code" href="classuart__wishbone__slave.html#aca7516cbd7b6a93eac24e720fc01760c">00013</a> <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#aca7516cbd7b6a93eac24e720fc01760c" title="Address input.">ADR_I0</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> <span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">1</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00014"></a><a class="code" href="classuart__wishbone__slave.html#ad423901fb91ee750587d52bd9ddb2001">00014</a> <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#ad423901fb91ee750587d52bd9ddb2001" title="Data Input 0.">DAT_I0</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> <span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00015"></a><a class="code" href="classuart__wishbone__slave.html#a5779ba7b1bb275d5e56907020420ca27">00015</a> <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#a5779ba7b1bb275d5e56907020420ca27" title="Data Output 0.">DAT_O0</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC_VECTOR</span> <span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">31</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00016"></a><a class="code" href="classuart__wishbone__slave.html#a32a749c5f0d113303c3de1fa917b8f56">00016</a> <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#a32a749c5f0d113303c3de1fa917b8f56" title="Write enable input.">WE_I</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00017"></a><a class="code" href="classuart__wishbone__slave.html#af3bb8cfb2912c0d4ce792bd6c53d6a4c">00017</a> <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#af3bb8cfb2912c0d4ce792bd6c53d6a4c" title="Strobe input (Works like a chip select)">STB_I</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00018"></a><a class="code" href="classuart__wishbone__slave.html#aeec8b0022ebb92b40f746bf13cf7319c">00018</a> <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#aeec8b0022ebb92b40f746bf13cf7319c" title="Ack output.">ACK_O</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC</span>;
<a name="l00019"></a>00019 <span class="keyword"></span>
<a name="l00020"></a>00020 <span class="keyword"> -- NON-WISHBONE Signals</span>
<a name="l00021"></a><a class="code" href="classuart__wishbone__slave.html#aafe347fe5fc89efa63d92386f60c5f50">00021</a> <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#aafe347fe5fc89efa63d92386f60c5f50" title="Uart serial input.">serial_in</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00022"></a><a class="code" href="classuart__wishbone__slave.html#ad55ceaa2b85f0ff8d37ba499fc620a61">00022</a> <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#ad55ceaa2b85f0ff8d37ba499fc620a61" title="Flag to indicate data avaible.">data_Avaible</a></span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00023"></a>00023 <span class="vhdlchar">serial_out</span> <span class="vhdlchar">:</span> <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>
<a name="l00024"></a>00024 <span class="vhdlchar">)</span>;
<a name="l00025"></a>00025 <span class="vhdlkeyword">end</span> <span class="vhdlchar">uart_wishbone_slave</span>;
<a name="l00026"></a>00026
<a name="l00029"></a><a class="code" href="classuart__wishbone__slave_1_1_behavioral.html">00029</a> <span class="vhdlkeyword">architecture</span> Behavioral <span class="vhdlkeyword">of</span> <a class="code" href="classuart__wishbone__slave.html">uart_wishbone_slave</a> is
<a name="l00030"></a><a class="code" href="classuart__wishbone__slave_1_1_behavioral.html#af10b00731d230bdd4222dc8e41e55ef0">00030</a> <span class="vhdlkeyword">component</span> <a class="code" href="classuart__control.html">uart_control</a> <span class="vhdlkeyword">is</span>
<a name="l00031"></a>00031 <span class="vhdlkeyword">Port</span> ( <a class="code" href="classuart__control.html#a9d3a5df2e98b99b950613d125404f7e7" title="Global reset.">rst</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00032"></a>00032 <a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00033"></a>00033 <a class="code" href="classuart__control.html#a5d0f1fd17d4ada84491cbbcdff7bd59c" title="Write enable.">WE</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00034"></a>00034 <a class="code" href="classuart__control.html#a26488fd3af03df7e52e89685254581d9" title="Register address.">reg_addr</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic_vector</span> (<span class="vhdllogic"></span><span class="vhdllogic">1</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00035"></a>00035 <a class="code" href="classuart__control.html#ae66e1f3b5a7b302a165fd87d2ebf8008" title="Start (Strobe)">start</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00036"></a>00036 <a class="code" href="classuart__control.html#a4772fc34e10751f941e00c7f532d3a51" title="Done (ACK)">done</a> : <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00037"></a>00037 <a class="code" href="classuart__control.html#a6a4e14f575e5b97e6af7829108a9cdb6" title="Data Input (Wishbone)">DAT_I</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic_vector</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00038"></a>00038 <a class="code" href="classuart__control.html#aa0441f210e0ee245a9ee654ee0ecb105" title="Data output (Wishbone)">DAT_O</a> : <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00039"></a>00039 <a class="code" href="classuart__control.html#ad78e0a527c5f5c8c3ffa83c438b6f61f" title="Signal to control the baud rate frequency.">baud_wait</a> : <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span> ((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00040"></a>00040 <a class="code" href="classuart__control.html#af5fbd616289aa28ef674937c72548374" title="1 Byte to be send to serial_transmitter">data_byte_tx</a> : <span class="vhdlkeyword">out</span> <span class="comment">std_logic_vector</span>((nBits<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00041"></a>00041 <a class="code" href="classuart__control.html#a938ea181dcf736513f3743dcf22dbf85" title="1 Byte to be received by serial_receiver">data_byte_rx</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic_vector</span>((nBits<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00042"></a>00042 <a class="code" href="classuart__control.html#af90e032a76aef85021ee288bbec12e11" title="Signal comming from serial_transmitter.">tx_data_sent</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00043"></a>00043 <a class="code" href="classuart__control.html#ac8df6578912d098bdb9f21cb0509fb63" title="Signal to start sending serial data...">tx_start</a> : <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00044"></a>00044 <a class="code" href="classuart__control.html#a665e6854e6570b00bd7d35db2049f54f" title="Reset Communication blocks.">rst_comm_blocks</a> : <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00045"></a>00045 <a class="code" href="classuart__control.html#a0f38cbc4316d4bba03252027fe0fabc7" title="Signal comming from serial_receiver.">rx_data_ready</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>);
<a name="l00046"></a>00046 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">component</span>;
<a name="l00047"></a>00047
<a name="l00048"></a><a class="code" href="classuart__wishbone__slave_1_1_behavioral.html#abe1057034c94a40f3d4c739676dea66c">00048</a> <span class="vhdlkeyword">component</span> <a class="code" href="classuart__communication__blocks.html">uart_communication_blocks</a> <span class="vhdlkeyword">is</span>
<a name="l00049"></a>00049 <span class="vhdlkeyword">Port</span> ( <a class="code" href="classuart__communication__blocks.html#a8951f9e34071cb1a681f0339ce4b63c4" title="Global reset.">rst</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00050"></a>00050 <a class="code" href="classuart__communication__blocks.html#a3fe846251d47f950195c2f54bd129c61" title="Global clock.">clk</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>;
<a name="l00051"></a>00051 <a class="code" href="classuart__communication__blocks.html#afa18bfa78951934bdb69cd7109c05aa3" title="Number of cycles to wait in order to generate desired baud.">cycle_wait_baud</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic_vector</span>((nBitsLarge<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00052"></a>00052 <a class="code" href="classuart__communication__blocks.html#a8cf74bfe6ea9ebd58f54385e60bcdb81" title="Byte to transmit.">byte_tx</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC_VECTOR</span> ((nBits<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00053"></a>00053 <a class="code" href="classuart__communication__blocks.html#af86c06321eda298448164ea4af314d9d" title="Byte to receive.">byte_rx</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC_VECTOR</span> ((nBits<span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span>) <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span>);
<a name="l00054"></a>00054 <a class="code" href="classuart__communication__blocks.html#a6911204ed04f303c8c0aeb381132178f" title="Indicate that byte has been sent.">data_sent_tx</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC</span>;
<a name="l00055"></a>00055 <a class="code" href="classuart__communication__blocks.html#a660ac404fdc70a7d4ac57286d0916c4a" title="Indicate that we got a byte.">data_received_rx</a> : <span class="vhdlkeyword">out</span> <span class="comment">STD_LOGIC</span>;
<a name="l00056"></a>00056 <a class="code" href="classuart__communication__blocks.html#a663f39bc9103a1c89116711a4d4f2fbc" title="Uart serial out.">serial_out</a> : <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
<a name="l00057"></a>00057 <a class="code" href="classuart__communication__blocks.html#ab5c23ea4f1cdfe2567b19e81909ecfc0" title="Uart serial in.">serial_in</a> : <span class="vhdlkeyword">in</span> <span class="comment">std_logic</span>;
<a name="l00058"></a>00058 <a class="code" href="classuart__communication__blocks.html#a2e4fb6cc48dc8f0ec684c80468ae6801" title="Initiate transmission.">start_tx</a> : <span class="vhdlkeyword">in</span> <span class="comment">STD_LOGIC</span>);
<a name="l00059"></a>00059 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">component</span>;
<a name="l00060"></a>00060 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">baud_wait</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdlchar">(</span><span class="vhdlchar">nBitsLarge</span><span class="vhdlchar">-</span><span class="vhdllogic"></span><span class="vhdllogic">1</span><span class="vhdlchar">)</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00061"></a>00061 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">tx_data_sent</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00062"></a>00062 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">tx_start</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00063"></a>00063 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">rst_comm_blocks</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00064"></a>00064 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">rx_data_ready</span> <span class="vhdlchar">:</span> <span class="comment">std_logic</span>;
<a name="l00065"></a>00065 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">data_byte_tx</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">7</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00066"></a>00066 <span class="vhdlkeyword">signal</span> <span class="vhdlchar">data_byte_rx</span> <span class="vhdlchar">:</span> <span class="comment">std_logic_vector</span><span class="vhdlchar">(</span><span class="vhdllogic"></span><span class="vhdllogic">7</span> <span class="vhdlkeyword">downto</span> <span class="vhdllogic"></span><span class="vhdllogic">0</span><span class="vhdlchar">)</span>;
<a name="l00067"></a>00067 <span class="vhdlkeyword">begin</span>
<a name="l00069"></a>00069 uUartControl : <a class="code" href="classuart__control.html">uart_control</a> <span class="vhdlkeyword">port</span> <span class="vhdlkeyword">map</span> (
<a name="l00070"></a>00070 <a class="code" href="classuart__control.html#a9d3a5df2e98b99b950613d125404f7e7" title="Global reset.">rst</a> => <a class="code" href="classuart__wishbone__slave.html#a4775682dc01dcbf48f20a731490ff2da" title="Reset Input.">RST_I</a>,
<a name="l00071"></a>00071 <a class="code" href="classuart__control.html#aaa012193baea07aae07ac241afc38d4e" title="Global clock.">clk</a> => <a class="code" href="classuart__wishbone__slave.html#aa26da3641303aaf250c88cbdf3d8a1a3" title="Clock Input.">CLK_I</a>,
<a name="l00072"></a>00072 <a class="code" href="classuart__control.html#a5d0f1fd17d4ada84491cbbcdff7bd59c" title="Write enable.">WE</a> => <a class="code" href="classuart__wishbone__slave.html#a32a749c5f0d113303c3de1fa917b8f56" title="Write enable input.">WE_I</a>,
<a name="l00073"></a>00073 <a class="code" href="classuart__control.html#a26488fd3af03df7e52e89685254581d9" title="Register address.">reg_addr</a> => <a class="code" href="classuart__wishbone__slave.html#aca7516cbd7b6a93eac24e720fc01760c" title="Address input.">ADR_I0</a>,
<a name="l00074"></a>00074 <a class="code" href="classuart__control.html#ae66e1f3b5a7b302a165fd87d2ebf8008" title="Start (Strobe)">start</a> => <a class="code" href="classuart__wishbone__slave.html#af3bb8cfb2912c0d4ce792bd6c53d6a4c" title="Strobe input (Works like a chip select)">STB_I</a>,
<a name="l00075"></a>00075 <a class="code" href="classuart__control.html#a4772fc34e10751f941e00c7f532d3a51" title="Done (ACK)">done</a> => <a class="code" href="classuart__wishbone__slave.html#aeec8b0022ebb92b40f746bf13cf7319c" title="Ack output.">ACK_O</a>,
<a name="l00076"></a>00076 <a class="code" href="classuart__control.html#a6a4e14f575e5b97e6af7829108a9cdb6" title="Data Input (Wishbone)">DAT_I</a> => <a class="code" href="classuart__wishbone__slave.html#ad423901fb91ee750587d52bd9ddb2001" title="Data Input 0.">DAT_I0</a>,
<a name="l00077"></a>00077 <a class="code" href="classuart__control.html#aa0441f210e0ee245a9ee654ee0ecb105" title="Data output (Wishbone)">DAT_O</a> => <a class="code" href="classuart__wishbone__slave.html#a5779ba7b1bb275d5e56907020420ca27" title="Data Output 0.">DAT_O0</a>,
<a name="l00078"></a>00078 <a class="code" href="classuart__control.html#ad78e0a527c5f5c8c3ffa83c438b6f61f" title="Signal to control the baud rate frequency.">baud_wait</a> => baud_wait ,
<a name="l00079"></a>00079 <a class="code" href="classuart__control.html#af5fbd616289aa28ef674937c72548374" title="1 Byte to be send to serial_transmitter">data_byte_tx</a> => data_byte_tx ,
<a name="l00080"></a>00080 <a class="code" href="classuart__control.html#a938ea181dcf736513f3743dcf22dbf85" title="1 Byte to be received by serial_receiver">data_byte_rx</a> => data_byte_rx ,
<a name="l00081"></a>00081 <a class="code" href="classuart__control.html#af90e032a76aef85021ee288bbec12e11" title="Signal comming from serial_transmitter.">tx_data_sent</a> => tx_data_sent ,
<a name="l00082"></a>00082 <a class="code" href="classuart__control.html#a665e6854e6570b00bd7d35db2049f54f" title="Reset Communication blocks.">rst_comm_blocks</a> => rst_comm_blocks ,
<a name="l00083"></a>00083 <a class="code" href="classuart__control.html#ac8df6578912d098bdb9f21cb0509fb63" title="Signal to start sending serial data...">tx_start</a> => tx_start ,
<a name="l00084"></a>00084 <a class="code" href="classuart__control.html#a0f38cbc4316d4bba03252027fe0fabc7" title="Signal comming from serial_receiver.">rx_data_ready</a> => rx_data_ready
<a name="l00085"></a>00085 <span class="vhdlchar">)</span>;
<a name="l00086"></a>00086
<a name="l00088"></a>00088 uUartCommunicationBlocks : <a class="code" href="classuart__communication__blocks.html">uart_communication_blocks</a> <span class="vhdlkeyword">port</span> <span class="vhdlkeyword">map</span> (
<a name="l00089"></a>00089 <a class="code" href="classuart__communication__blocks.html#a8951f9e34071cb1a681f0339ce4b63c4" title="Global reset.">rst</a> => rst_comm_blocks,
<a name="l00090"></a>00090 <a class="code" href="classuart__communication__blocks.html#a3fe846251d47f950195c2f54bd129c61" title="Global clock.">clk</a> => <a class="code" href="classuart__wishbone__slave.html#aa26da3641303aaf250c88cbdf3d8a1a3" title="Clock Input.">CLK_I</a>,
<a name="l00091"></a>00091 <a class="code" href="classuart__communication__blocks.html#afa18bfa78951934bdb69cd7109c05aa3" title="Number of cycles to wait in order to generate desired baud.">cycle_wait_baud</a> => baud_wait,
<a name="l00092"></a>00092 <a class="code" href="classuart__communication__blocks.html#a8cf74bfe6ea9ebd58f54385e60bcdb81" title="Byte to transmit.">byte_tx</a> => data_byte_tx,
<a name="l00093"></a>00093 <a class="code" href="classuart__communication__blocks.html#af86c06321eda298448164ea4af314d9d" title="Byte to receive.">byte_rx</a> => data_byte_rx,
<a name="l00094"></a>00094 <a class="code" href="classuart__communication__blocks.html#a6911204ed04f303c8c0aeb381132178f" title="Indicate that byte has been sent.">data_sent_tx</a> => tx_data_sent ,
<a name="l00095"></a>00095 <a class="code" href="classuart__communication__blocks.html#a660ac404fdc70a7d4ac57286d0916c4a" title="Indicate that we got a byte.">data_received_rx</a> => rx_data_ready,
<a name="l00096"></a>00096 <a class="code" href="classuart__communication__blocks.html#a663f39bc9103a1c89116711a4d4f2fbc" title="Uart serial out.">serial_out</a> => serial_out ,
<a name="l00097"></a>00097 <a class="code" href="classuart__communication__blocks.html#ab5c23ea4f1cdfe2567b19e81909ecfc0" title="Uart serial in.">serial_in</a> => <a class="code" href="classuart__wishbone__slave.html#aafe347fe5fc89efa63d92386f60c5f50" title="Uart serial input.">serial_in</a> ,
<a name="l00098"></a>00098 <a class="code" href="classuart__communication__blocks.html#a2e4fb6cc48dc8f0ec684c80468ae6801" title="Initiate transmission.">start_tx</a> => tx_start
<a name="l00099"></a>00099 <span class="vhdlchar">)</span>;
<a name="l00100"></a>00100
<a name="l00101"></a>00101 <span class="vhdlchar"><a class="code" href="classuart__wishbone__slave.html#ad55ceaa2b85f0ff8d37ba499fc620a61" title="Flag to indicate data avaible.">data_Avaible</a></span> <span class="vhdlchar"><=</span> <span class="vhdlchar">rx_data_ready</span>;
<a name="l00102"></a>00102
<a name="l00103"></a>00103 <span class="vhdlkeyword">end</span> <span class="vhdlchar">Behavioral</span>;
<a name="l00104"></a>00104
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