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\section{Behavioral Architecture Reference}
\label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral}\index{Behavioral@{Behavioral}}
 
 
Declaring the components (\doxyref{S\-Y\-C0001a}{p.}{class_s_y_c0001a}, \doxyref{S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R}{p.}{class_s_e_r_i_a_l_m_a_s_t_e_r}, \doxyref{uart\-\_\-wishbone\-\_\-slave}{p.}{classuart__wishbone__slave})  
 
 
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\subsection*{Components}
 \begin{DoxyCompactItemize}
\item 
{\bf S\-Y\-C0001a}  {\bfseries }  
\begin{DoxyCompactList}\small\item\em Clock output. \end{DoxyCompactList}\item 
{\bf S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R}  {\bfseries }  
\begin{DoxyCompactList}\small\item\em Ack input. \end{DoxyCompactList}\item 
{\bf uart\-\_\-wishbone\-\_\-slave}  {\bfseries }  
\begin{DoxyCompactList}\small\item\em Reset Input. \end{DoxyCompactList}\end{DoxyCompactItemize}
\subsection*{Signals}
 \begin{DoxyCompactItemize}
\item 
{\bf C\-L\-K} {\bfseries std\-\_\-logic } \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_acef6c685139cf878735d133cbb1c3f39}
 
\item 
{\bf R\-S\-T} {\bfseries std\-\_\-logic } \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_a1b2ce329025fb7093ff70e636d12a866}
 
\item 
{\bf A\-C\-K} {\bfseries std\-\_\-logic } \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_a390d1a631f1b4e3a4e6c8100a89d2a1a}
 
\item 
{\bf W\-E} {\bfseries std\-\_\-logic } \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_ac80819cc19e23b048a63969ff1734fe3}
 
\item 
{\bf S\-T\-B} {\bfseries std\-\_\-logic } \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_abdf56a973f6d5e4f89aaeda24c14daae}
 
\item 
{\bf A\-D\-R} {\bfseries std\-\_\-logic\-\_\-vector (   1    downto    0  ) } \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_abadff3227c7c9a2efb08edb0c8ad8748}
 
\item 
{\bf data\-I} {\bfseries std\-\_\-logic\-\_\-vector (   31    downto    0  ) } \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_aed15a1c21fea27515d3bb53207f39a32}
 
\item 
{\bf data\-O} {\bfseries std\-\_\-logic\-\_\-vector (   31    downto    0  ) } \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_aa0fa98bb667fa3676c31b4542a34b28a}
 
\end{DoxyCompactItemize}
\subsection*{Instantiations}
 \begin{DoxyCompactItemize}
\item 
{\bf u\-Sys\-Con}  {\bfseries S\-Y\-C0001a}   \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_addc89a1043fac3e419f545918b00304b}
 
\begin{DoxyCompactList}\small\item\em Instantiate \doxyref{S\-Y\-C0001a}{p.}{class_s_y_c0001a}. \end{DoxyCompactList}\item 
{\bf u\-Master\-Serial}  {\bfseries S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R}   \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_a17d29dc89d37b4f2942037816f9095f9}
 
\begin{DoxyCompactList}\small\item\em Instantiate \doxyref{S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R}{p.}{class_s_e_r_i_a_l_m_a_s_t_e_r}. \end{DoxyCompactList}\item 
{\bf u\-Uart\-Wishbone\-Slave}  {\bfseries uart\-\_\-wishbone\-\_\-slave}   \label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_a869bee07e49a71e28b889f35f114c40f}
 
\begin{DoxyCompactList}\small\item\em Instantiate \doxyref{uart\-\_\-wishbone\-\_\-slave}{p.}{classuart__wishbone__slave}. \end{DoxyCompactList}\end{DoxyCompactItemize}
 
 
\subsection{Detailed Description}
Declaring the components (\doxyref{S\-Y\-C0001a}{p.}{class_s_y_c0001a}, \doxyref{S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R}{p.}{class_s_e_r_i_a_l_m_a_s_t_e_r}, \doxyref{uart\-\_\-wishbone\-\_\-slave}{p.}{classuart__wishbone__slave}) 
 
Just instantiate and connect the various components 
 
Definition at line 22 of file I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P.\-vhd.
 
 
 
\subsection{Member Data Documentation}
\index{I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P\-::\-Behavioral@{I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P\-::\-Behavioral}!S\-Y\-C0001a@{S\-Y\-C0001a}}
\index{S\-Y\-C0001a@{S\-Y\-C0001a}!INTERCON_P2P::Behavioral@{I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P\-::\-Behavioral}}
\subsubsection[{S\-Y\-C0001a}]{\setlength{\rightskip}{0pt plus 5cm}{\bf S\-Y\-C0001a} {\bfseries  } \hspace{0.3cm}{\ttfamily  [Component]}}\label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_a99b85cc71dbbaa06e16f4d4351530462}
 
 
Clock output. 
 
Reset output Clock input Reset input 
 
Definition at line 23 of file I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P.\-vhd.
 
\index{I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P\-::\-Behavioral@{I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P\-::\-Behavioral}!S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R@{S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R}}
\index{S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R@{S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R}!INTERCON_P2P::Behavioral@{I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P\-::\-Behavioral}}
\subsubsection[{S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R}]{\setlength{\rightskip}{0pt plus 5cm}{\bf S\-E\-R\-I\-A\-L\-M\-A\-S\-T\-E\-R} {\bfseries  } \hspace{0.3cm}{\ttfamily  [Component]}}\label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_a3eba7772cc5be92821da2ebda4b73fae}
 
 
Ack input. 
 
Address output Clock input Cycle output Data input Data output Reset input Select output Strobe output (Works like a chip select) Write enable Signal byte received (Used to debug on the out leds) 
 
Definition at line 34 of file I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P.\-vhd.
 
\index{I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P\-::\-Behavioral@{I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P\-::\-Behavioral}!uart\-\_\-wishbone\-\_\-slave@{uart\-\_\-wishbone\-\_\-slave}}
\index{uart\-\_\-wishbone\-\_\-slave@{uart\-\_\-wishbone\-\_\-slave}!INTERCON_P2P::Behavioral@{I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P\-::\-Behavioral}}
\subsubsection[{uart\-\_\-wishbone\-\_\-slave}]{\setlength{\rightskip}{0pt plus 5cm}{\bf uart\-\_\-wishbone\-\_\-slave} {\bfseries  } \hspace{0.3cm}{\ttfamily  [Component]}}\label{class_i_n_t_e_r_c_o_n___p2_p_1_1_behavioral_abc849ae7612bb6c8206d5bb023aee9b7}
 
 
Reset Input. 
 
Clock Input Address input Data Input 0 Data Output 0 Write enable input Strobe input (Works like a chip select) Ack output Uart serial input Flag to indicate data avaible Uart serial output 
 
Definition at line 53 of file I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P.\-vhd.
 
 
 
The documentation for this class was generated from the following file\-:\begin{DoxyCompactItemize}
\item 
E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf I\-N\-T\-E\-R\-C\-O\-N\-\_\-\-P2\-P.\-vhd}\end{DoxyCompactItemize}