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\section{behavior Architecture Reference}
\label{classtest_divisor_1_1behavior}\index{behavior@{behavior}}
 
 
Test divisor module.  
 
 
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\subsection*{Processes}
 \begin{DoxyCompactItemize}
\item 
{\bf clk\-\_\-process}{\bfseries  (  )}\label{classtest_divisor_1_1behavior_ac5bb218131b813f7908ec89476b31fca}
 
\item 
{\bf stim\-\_\-proc}{\bfseries  (  )}\label{classtest_divisor_1_1behavior_ad2efa6785cff833c341e27596b21aeb5}
 
\end{DoxyCompactItemize}
\subsection*{Components}
 \begin{DoxyCompactItemize}
\item 
{\bf divisor}  {\bfseries }  
\begin{DoxyCompactList}\small\item\em Reset input. \end{DoxyCompactList}\end{DoxyCompactItemize}
\subsection*{Constants}
 \begin{DoxyCompactItemize}
\item 
{\bf clk\-\_\-period} {\bfseries time  \-:=  10  ns } \label{classtest_divisor_1_1behavior_aee75ea6d5c1621041dff5db20cba7e70}
 
\end{DoxyCompactItemize}
\subsection*{Signals}
 \begin{DoxyCompactItemize}
\item 
{\bf rst} {\bfseries std\-\_\-logic  \-:= '  0  ' } \label{classtest_divisor_1_1behavior_a513fa2f18065f5d31a856b5a7268e6be}
 
\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item 
{\bf clk} {\bfseries std\-\_\-logic  \-:= '  0  ' } \label{classtest_divisor_1_1behavior_ad8d4742a7eb2e3d3a95e8c0c37d14ed2}
 
\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item 
{\bf numerator} {\bfseries std\-\_\-logic\-\_\-vector (  ( n\-Bits\-Large -\/   1  )    downto    0  )  \-:= (  others  = $>$ '  0  '  ) } \label{classtest_divisor_1_1behavior_ab6d0f470182dc53c3c65afad4c78bddd}
 
\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item 
{\bf divident} {\bfseries std\-\_\-logic\-\_\-vector (  ( n\-Bits\-Large -\/   1  )    downto    0  )  \-:= (  others  = $>$ '  0  '  ) } \label{classtest_divisor_1_1behavior_a45d3fd79b3d4a9c68e45d5bfd00d1fc7}
 
\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item 
{\bf quotient} {\bfseries std\-\_\-logic\-\_\-vector (  ( n\-Bits\-Large -\/   1  )    downto    0  ) } \label{classtest_divisor_1_1behavior_a0a9f54386a9ef858f70c32ccceb1ab0e}
 
\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item 
{\bf reminder} {\bfseries std\-\_\-logic\-\_\-vector (  ( n\-Bits\-Large -\/   1  )    downto    0  ) } \label{classtest_divisor_1_1behavior_a4192e4decb5e0fff313ed7578a1fe6a5}
 
\begin{DoxyCompactList}\small\item\em Signal to connect with U\-U\-T. \end{DoxyCompactList}\item 
{\bf done} {\bfseries std\-\_\-logic } \label{classtest_divisor_1_1behavior_a52b926bb7d7b6f608cf22d09d17be95a}
 
\end{DoxyCompactItemize}
\subsection*{Instantiations}
 \begin{DoxyCompactItemize}
\item 
{\bf uut}  {\bfseries divisor}   \label{classtest_divisor_1_1behavior_a1619316ad715601eb5d3559db829ac05}
 
\begin{DoxyCompactList}\small\item\em Instantiate the Unit Under Test (U\-U\-T) \end{DoxyCompactList}\end{DoxyCompactItemize}
 
 
\subsection{Detailed Description}
Test divisor module. 
 
Calculate some divisions and verify if we have the right value 
 
Definition at line 17 of file test\-Divisor.\-vhd.
 
 
 
\subsection{Member Data Documentation}
\index{test\-Divisor\-::behavior@{test\-Divisor\-::behavior}!divisor@{divisor}}
\index{divisor@{divisor}!testDivisor::behavior@{test\-Divisor\-::behavior}}
\subsubsection[{divisor}]{\setlength{\rightskip}{0pt plus 5cm}{\bf divisor} {\bfseries  } \hspace{0.3cm}{\ttfamily  [Component]}}\label{classtest_divisor_1_1behavior_ab31bbf4e04b601f06da44e54e616cc99}
 
 
Reset input. 
 
Clock input Division result (32 bits) Reminder result (32 bits) Numerator (32 bits) \char`\"{}\-Divide by\char`\"{} number (32 bits) 
 
Definition at line 21 of file test\-Divisor.\-vhd.
 
 
 
The documentation for this class was generated from the following files\-:\begin{DoxyCompactItemize}
\item 
E\-:/uart\-\_\-block/hdl/ise\-Project/{\bf test\-Divisor.\-vhd}\end{DoxyCompactItemize}