Subversion Repositories usb_fpga_1_15

memtest
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This example implements a FIFO using DDR SDRAM.

The input data is generated by a test pattern generator and is written
continuously  to the SDRAM FIFO. This FIFO is read out continuously and
the data is written to the EZ-USB using the slave FIFO interface of the
EZ-USB. The host PC's reads out this data via USB and verifies it.

Use this example as starting point for high speed (uninterrupted)
data acquisition applications.

The directories "fpga" and "fpga-11" contain the project files for
Xilinx ISE versions 12.2 and 11.4, respectively.