Subversion Repositories usb_fpga_1_15

NET "FXCLK" TNM_NET = "FXCLK";
TIMESPEC "TS_FXCLK" = PERIOD "FXCLK" 20.833333 ns HIGH 50 %;
NET "FXCLK"  LOC = "J16" | IOSTANDARD = LVCMOS33 ;

NET "IFCLK" TNM_NET = "IFCLK";
TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20 ns HIGH 50 %;
NET "IFCLK"  LOC = "J14" | IOSTANDARD = LVCMOS33 ;

NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK_IFCLK" = FROM "CLK" TO "IFCLK" 3ns DATAPATHONLY;
TIMESPEC "TS_IFCLK_CLK" = FROM "IFCLK" TO "CLK" 3ns DATAPATHONLY;

NET "RESET_IN" LOC = "R11" | IOSTANDARD = LVCMOS33 ;                    # PA0
NET "PA3"  LOC = "T3" | IOSTANDARD = LVCMOS33 ;                         # PA3

NET "SLOE"  LOC = "H13" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;          # PA2
NET "FIFOADR0"  LOC = "T11" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;      # PA4
NET "FIFOADR1"  LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;      # PA5
NET "PKTEND"  LOC = "T5" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;         # PA6

NET "FD<0>"      LOC = "D16" | IOSTANDARD = LVCMOS33 ;           # PB0/FD0
NET "FD<1>"     LOC = "F15" | IOSTANDARD = LVCMOS33 ;           # PB1/FD1
NET "FD<2>"     LOC = "E15" | IOSTANDARD = LVCMOS33 ;           # PB2/FD2
NET "FD<3>"     LOC = "D14" | IOSTANDARD = LVCMOS33 ;           # PB3/FD3
NET "FD<4>"     LOC = "F13" | IOSTANDARD = LVCMOS33 ;           # PB4/FD4
NET "FD<5>"     LOC = "E12" | IOSTANDARD = LVCMOS33 ;           # PB5/FD5
NET "FD<6>"     LOC = "F12" | IOSTANDARD = LVCMOS33 ;           # PB6/FD6
NET "FD<7>"     LOC = "G12" | IOSTANDARD = LVCMOS33 ;           # PB7/FD7
NET "FD<8>"     LOC = "H14" | IOSTANDARD = LVCMOS33 ;           # PD0/FD8
NET "FD<9>"     LOC = "J11" | IOSTANDARD = LVCMOS33 ;           # PD1/FD9
NET "FD<10>"    LOC = "J12" | IOSTANDARD = LVCMOS33 ;           # PD2/FD10
NET "FD<11>"    LOC = "J13" | IOSTANDARD = LVCMOS33 ;           # PD3/FD11
NET "FD<12>"    LOC = "K12" | IOSTANDARD = LVCMOS33 ;           # PD4/FD12
NET "FD<13>"    LOC = "K15" | IOSTANDARD = LVCMOS33 ;           # PD5/FD13
NET "FD<14>"    LOC = "K16" | IOSTANDARD = LVCMOS33 ;           # PD6/FD14
NET "FD<15>"    LOC = "M14" | IOSTANDARD = LVCMOS33 ;           # PD7/FD15

NET "FLAGB"     LOC = "G16" | IOSTANDARD = LVCMOS33 ;           # CTL1/FLAGB

NET "SLRD"      LOC = "H16" | IOSTANDARD = LVCMOS33 ;           # RDY0/SLRD
NET "SLWR"      LOC = "H15" | IOSTANDARD = LVCMOS33 ;           # RDY1/SLWR


NET "LED1<0>"    LOC = "B16" | IOSTANDARD = LVCMOS33 | DRIVE=12 ;                # A6 / B16~IO_L29N_A22_M1A14_1
NET "LED1<1>"   LOC = "C16" | IOSTANDARD = LVCMOS33 | DRIVE=12 ;                # B6 / C16~IO_L33N_A14_M1A4_1
NET "LED1<2>"   LOC = "B15" | IOSTANDARD = LVCMOS33 | DRIVE=12 ;                # A7 / B15~IO_L29P_A23_M1A13_1
NET "LED1<3>"   LOC = "C15" | IOSTANDARD = LVCMOS33 | DRIVE=12 ;                # B7 / C15~IO_L33P_A15_M1A10_1
NET "LED1<4>"   LOC = "A14" | IOSTANDARD = LVCMOS33 | DRIVE=12 ;                # A8 / A14~IO_L65N_SCP2_0
NET "LED1<5>"   LOC = "B14" | IOSTANDARD = LVCMOS33 | DRIVE=12 ;                # B8 / B14~IO_L65P_SCP3_0
NET "LED1<6>"   LOC = "A13" | IOSTANDARD = LVCMOS33 | DRIVE=12 ;                # A9 / A13~IO_L63N_SCP6_0
NET "LED1<7>"   LOC = "C13" | IOSTANDARD = LVCMOS33 | DRIVE=12 ;                # B9 / C13~IO_L63P_SCP7_0
NET "LED1<8>"   LOC = "A12" | IOSTANDARD = LVCMOS33 | DRIVE=12 ;                # A10 / A12~IO_L62N_VREF_0
NET "LED1<9>"   LOC = "B12" | IOSTANDARD = LVCMOS33 | DRIVE=12 ;                # B10 / B12~IO_L62P_0


############################################################################
# VCC AUX VOLTAGE 
############################################################################
CONFIG VCCAUX=2.5;

############################################################################
## Memory Controller 3                               
## Memory Device: DDR_SDRAM->MT46V32M16XX-5B-IT 
## Frequency: 200 MHz
## Time Period: 5000 ps
## Supported Part Numbers: MT46V32M16BN-5B-IT
############################################################################

############################################################################
## I/O TERMINATION                                                          
############################################################################
NET "mcb3_dram_dq[*]"                                 IN_TERM = UNTUNED_SPLIT_50;
NET "mcb3_dram_dqs"                                   IN_TERM = UNTUNED_SPLIT_50;
NET "mcb3_dram_udqs"                                  IN_TERM = UNTUNED_SPLIT_50;

NET  "mcb3_dram_a[*]"                                 OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ba[*]"                                OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ck"                                   OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ck_n"                                 OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_cke"                                  OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ras_n"                                OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_cas_n"                                OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_we_n"                                 OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_dm"                                   OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_udm"                                  OUT_TERM = UNTUNED_50; 

############################################################################
# I/O STANDARDS 
############################################################################
# NET  "mcb3_dram_dq[*]"                               IOSTANDARD = LVCMOS25;
# NET  "mcb3_dram_dqs"                                 IOSTANDARD = LVCMOS25;
# NET  "mcb3_dram_udqs"                                IOSTANDARD = LVCMOS25;
# NET  "mcb3_rzq"                                      IOSTANDARD = LVCMOS25;
# NET  "mcb3_zio"                                      IOSTANDARD = LVCMOS25;
NET  "mcb3_dram_dq[*]"                               IOSTANDARD = SSTL2_II;
NET  "mcb3_dram_dqs"                                 IOSTANDARD = SSTL2_II;
NET  "mcb3_dram_udqs"                                IOSTANDARD = SSTL2_II;
NET  "mcb3_rzq"                                      IOSTANDARD = SSTL2_II;
NET  "mcb3_zio"                                      IOSTANDARD = SSTL2_II;

NET  "mcb3_dram_a[*]"                                IOSTANDARD = SSTL2_II;
NET  "mcb3_dram_ba[*]"                               IOSTANDARD = SSTL2_II;
NET  "mcb3_dram_ck"                                  IOSTANDARD = DIFF_SSTL2_II;
NET  "mcb3_dram_ck_n"                                IOSTANDARD = DIFF_SSTL2_II;
NET  "mcb3_dram_cke"                                 IOSTANDARD = SSTL2_II;
NET  "mcb3_dram_ras_n"                               IOSTANDARD = SSTL2_II;
NET  "mcb3_dram_cas_n"                               IOSTANDARD = SSTL2_II;
NET  "mcb3_dram_we_n"                                IOSTANDARD = SSTL2_II;
NET  "mcb3_dram_dm"                                  IOSTANDARD = SSTL2_II;
NET  "mcb3_dram_udm"                                 IOSTANDARD = SSTL2_II;


############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################

NET  "mcb3_dram_dq[4]"                           LOC = "F2" ;
NET  "mcb3_dram_dq[5]"                           LOC = "F1" ;
NET  "mcb3_dram_dq[6]"                           LOC = "G3" ;
NET  "mcb3_dram_dq[7]"                           LOC = "G1" ;
NET  "mcb3_dram_dq[2]"                           LOC = "J3" ;
NET  "mcb3_dram_dq[3]"                           LOC = "J1" ;
NET  "mcb3_dram_dq[0]"                           LOC = "K2" ;
NET  "mcb3_dram_dq[1]"                           LOC = "K1" ;

NET  "mcb3_dram_dq[8]"                           LOC = "L3" ;
NET  "mcb3_dram_dq[9]"                           LOC = "L1" ;
NET  "mcb3_dram_dq[10]"                          LOC = "M2" ;
NET  "mcb3_dram_dq[11]"                          LOC = "M1" ;
NET  "mcb3_dram_dq[12]"                          LOC = "P2" ;
NET  "mcb3_dram_dq[13]"                          LOC = "P1" ;
NET  "mcb3_dram_dq[14]"                          LOC = "R2" ;
NET  "mcb3_dram_dq[15]"                          LOC = "R1" ;

NET  "mcb3_dram_dqs"                             LOC = "H2" ;
NET  "mcb3_dram_udqs"                            LOC = "N3" ;

NET  "mcb3_dram_ba[0]"                           LOC = "C3" ;
NET  "mcb3_dram_ba[1]"                           LOC = "C2" ;

NET  "mcb3_dram_a[0]"                            LOC = "K5" ;
NET  "mcb3_dram_a[1]"                            LOC = "K6" ;
NET  "mcb3_dram_a[2]"                            LOC = "D1" ;
NET  "mcb3_dram_a[3]"                            LOC = "L4" ;
NET  "mcb3_dram_a[4]"                            LOC = "G5" ;
NET  "mcb3_dram_a[5]"                            LOC = "H4" ;
NET  "mcb3_dram_a[6]"                            LOC = "H3" ;
NET  "mcb3_dram_a[7]"                            LOC = "D3" ;
NET  "mcb3_dram_a[8]"                            LOC = "B2" ;
NET  "mcb3_dram_a[9]"                            LOC = "A2" ;
NET  "mcb3_dram_a[10]"                           LOC = "G6" ;
NET  "mcb3_dram_a[11]"                           LOC = "E3" ;
NET  "mcb3_dram_a[12]"                           LOC = "F3" ;

NET  "mcb3_dram_dm"                              LOC = "J4" ;
NET  "mcb3_dram_udm"                             LOC = "K3" ;

NET  "mcb3_dram_ras_n"                           LOC = "J6" ;
NET  "mcb3_dram_cas_n"                           LOC = "H5" ;
NET  "mcb3_dram_we_n"                            LOC = "C1" ;

NET  "mcb3_dram_ck"                              LOC = "E2" ;
NET  "mcb3_dram_ck_n"                            LOC = "E1" ;
NET  "mcb3_dram_cke"                             LOC = "F4" ;

# NC pins 
NET  "mcb3_rzq"                                  LOC = "M4" ;
NET  "mcb3_zio"                                  LOC = "M5" ;