Subversion Repositories usb_fpga_1_15

# CLKOUT/FXCLK 
NET "clk" TNM_NET = "clk";
TIMESPEC "ts_clk" = PERIOD "clk" 48 MHz HIGH 50 %;
NET "clk"  LOC = "J16" | IOSTANDARD = LVCMOS33 ;

NET "PB<0>"      LOC = "D16" | IOSTANDARD = LVCMOS33 ;           # PB0/FD0
NET "PB<1>"     LOC = "F15" | IOSTANDARD = LVCMOS33 ;           # PB1/FD1
NET "PB<2>"     LOC = "E15" | IOSTANDARD = LVCMOS33 ;           # PB2/FD2
NET "PB<3>"     LOC = "D14" | IOSTANDARD = LVCMOS33 ;           # PB3/FD3
NET "PB<4>"     LOC = "F13" | IOSTANDARD = LVCMOS33 ;           # PB4/FD4
NET "PB<5>"     LOC = "E12" | IOSTANDARD = LVCMOS33 ;           # PB5/FD5
NET "PB<6>"     LOC = "F12" | IOSTANDARD = LVCMOS33 ;           # PB6/FD6
NET "PB<7>"     LOC = "G12" | IOSTANDARD = LVCMOS33 ;           # PB7/FD7

NET "PC<0>"      LOC = "P10" | IOSTANDARD = LVCMOS33 ;           # PC0/GPIFADR0
NET "PC<1>"     LOC = "N12" | IOSTANDARD = LVCMOS33 ;           # PC1/GPIFADR1
NET "PC<2>"     LOC = "P12" | IOSTANDARD = LVCMOS33 ;           # PC2/GPIFADR2
NET "PC<3>"     LOC = "N5" | IOSTANDARD = LVCMOS33 ;            # PC3/GPIFADR3
NET "PC<4>"     LOC = "P5" | IOSTANDARD = LVCMOS33 ;            # PC4/GPIFADR4
NET "PC<5>"     LOC = "L8" | IOSTANDARD = LVCMOS33 ;            # PC5/GPIFADR5
NET "PC<6>"     LOC = "L7" | IOSTANDARD = LVCMOS33 ;            # PC6/GPIFADR6
NET "PC<7>"     LOC = "R5" | IOSTANDARD = LVCMOS33 ;            # PC7/GPIFADR7