Subversion Repositories usb_fpga_2_04

NET "FXCLK" TNM_NET = "FXCLK";
TIMESPEC "TS_FXCLK" = PERIOD "FXCLK" 20.83333 ns HIGH 50 %;
NET "FXCLK"  LOC = "L22" | IOSTANDARD = LVCMOS33 ;

NET "IFCLK" TNM_NET = "IFCLK";
TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20 ns HIGH 50 %;
NET "IFCLK"  LOC = "K20" | IOSTANDARD = LVCMOS33 ;

NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK_IFCLK" = FROM "CLK" TO "IFCLK" 3ns DATAPATHONLY;
TIMESPEC "TS_IFCLK_CLK" = FROM "IFCLK" TO "CLK" 3ns DATAPATHONLY;

NET "SLOE"  LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;          # PA2
NET "FIFOADR0"  LOC = "W17" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;      # PA4
NET "FIFOADR1"  LOC = "Y18" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;      # PA5
NET "PKTEND"  LOC = "AB5" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;        # PA6
NET "RESET_IN" LOC = "AB17" | IOSTANDARD = LVCMOS33 ;                   # PA7

NET "PC0"  LOC = "G20" | IOSTANDARD = LVCMOS33 ;

NET "fd<0>"  LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
NET "fd<1>"  LOC = "V13" | IOSTANDARD = LVCMOS33 ;
NET "fd<2>"  LOC = "W13" | IOSTANDARD = LVCMOS33 ;
NET "fd<3>"  LOC = "AA8" | IOSTANDARD = LVCMOS33 ;
NET "fd<4>"  LOC = "AB8" | IOSTANDARD = LVCMOS33 ;
NET "fd<5>"  LOC = "W6" | IOSTANDARD = LVCMOS33 ;
NET "fd<6>"  LOC = "Y6" | IOSTANDARD = LVCMOS33 ;
NET "fd<7>"  LOC = "Y9" | IOSTANDARD = LVCMOS33 ;
NET "fd<8>"  LOC = "V21" | IOSTANDARD = LVCMOS33 ;
NET "fd<9>"  LOC = "V22" | IOSTANDARD = LVCMOS33 ;
NET "fd<10>"  LOC = "U20" | IOSTANDARD = LVCMOS33 ;
NET "fd<11>"  LOC = "U22" | IOSTANDARD = LVCMOS33 ;
NET "fd<12>"  LOC = "R20" | IOSTANDARD = LVCMOS33 ;
NET "fd<13>"  LOC = "R22" | IOSTANDARD = LVCMOS33 ;
NET "fd<14>"  LOC = "P18" | IOSTANDARD = LVCMOS33 ;
NET "fd<15>"  LOC = "P19" | IOSTANDARD = LVCMOS33 ;

NET "FLAGB"  LOC = "F19" | IOSTANDARD = LVCMOS33 ;

NET "SLRD"  LOC = "N22" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "SLWR"  LOC = "M22" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;


############################################################################
# VCC AUX VOLTAGE 
############################################################################
CONFIG VCCAUX=2.5;

############################################################################
## Memory Controller 3                               
## Memory Device: DDR_SDRAM->MT46V32M16XX-5B-IT 
## Frequency: 200 MHz
## Time Period: 5000 ps
## Supported Part Numbers: MT46V32M16BN-5B-IT
############################################################################
CONFIG MCB_PERFORMANCE= EXTENDED;

############################################################################
## I/O TERMINATION                                                          
############################################################################
#NET "mcb3_dram_dq[*]"                                 IN_TERM = UNTUNED_SPLIT_50;
#NET "mcb3_dram_dqs"                                   IN_TERM = UNTUNED_SPLIT_50;
#NET "mcb3_dram_dqs_n"                                 IN_TERM = UNTUNED_SPLIT_50;
#NET "mcb3_dram_udqs"                                  IN_TERM = UNTUNED_SPLIT_50;
#NET "mcb3_dram_udqs_n"                                IN_TERM = UNTUNED_SPLIT_50;
NET "mcb3_dram_dq[*]"                                 IN_TERM = NONE;
NET "mcb3_dram_dqs"                                   IN_TERM = NONE;
NET "mcb3_dram_dqs_n"                                 IN_TERM = NONE;
NET "mcb3_dram_udqs"                                  IN_TERM = NONE;
NET "mcb3_dram_udqs_n"                                IN_TERM = NONE;

#NET  "mcb3_dram_dq[*]"                                OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_a[*]"                                 OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ba[*]"                                OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ck"                                   OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ck_n"                                 OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_cke"                                  OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_ras_n"                                OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_cas_n"                                OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_we_n"                                 OUT_TERM = UNTUNED_50; 
#NET  "mcb3_dram_odt"                                  OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_dm"                                   OUT_TERM = UNTUNED_50; 
NET  "mcb3_dram_udm"                                  OUT_TERM = UNTUNED_50; 

############################################################################
# I/O STANDARDS 
############################################################################
NET  "mcb3_dram_dq[*]"                               IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_a[*]"                                IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_ba[*]"                               IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_dqs"                                 IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_udqs"                                IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_dqs_n"                               IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_udqs_n"                              IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_ck"                                  IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_ck_n"                                IOSTANDARD = DIFF_SSTL18_II;
NET  "mcb3_dram_cke"                                 IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_ras_n"                               IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_cas_n"                               IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_we_n"                                IOSTANDARD = SSTL18_II;
#NET  "mcb3_dram_odt"                                 IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_dm"                                  IOSTANDARD = SSTL18_II;
NET  "mcb3_dram_udm"                                 IOSTANDARD = SSTL18_II;
NET  "mcb3_rzq"                                      IOSTANDARD = SSTL18_II;
NET  "mcb3_zio"                                      IOSTANDARD = SSTL18_II;

############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################
NET  "mcb3_dram_a[0]"                            LOC = "M5" ;
NET  "mcb3_dram_a[10]"                           LOC = "K6" ;
NET  "mcb3_dram_a[11]"                           LOC = "B1" ;
NET  "mcb3_dram_a[12]"                           LOC = "J4" ;
NET  "mcb3_dram_a[1]"                            LOC = "L4" ;
NET  "mcb3_dram_a[2]"                            LOC = "K3" ;
NET  "mcb3_dram_a[3]"                            LOC = "M4" ;
NET  "mcb3_dram_a[4]"                            LOC = "K5" ;
NET  "mcb3_dram_a[5]"                            LOC = "G3" ;
NET  "mcb3_dram_a[6]"                            LOC = "G1" ;
NET  "mcb3_dram_a[7]"                            LOC = "K4" ;
NET  "mcb3_dram_a[8]"                            LOC = "C3" ;
NET  "mcb3_dram_a[9]"                            LOC = "C1" ;
NET  "mcb3_dram_ba[0]"                           LOC = "E3" ;
NET  "mcb3_dram_ba[1]"                           LOC = "E1" ;
NET  "mcb3_dram_ba[2]"                           LOC = "D1" ;
NET  "mcb3_dram_cas_n"                           LOC = "P3" ;
NET  "mcb3_dram_ck"                              LOC = "F2" ;
NET  "mcb3_dram_ck_n"                            LOC = "F1" ;
NET  "mcb3_dram_cke"                             LOC = "J6" ;
NET  "mcb3_dram_dm"                              LOC = "H1" ;
NET  "mcb3_dram_dq[0]"                           LOC = "N3" ;
NET  "mcb3_dram_dq[10]"                          LOC = "R3" ;
NET  "mcb3_dram_dq[11]"                          LOC = "R1" ;
NET  "mcb3_dram_dq[12]"                          LOC = "U3" ;
NET  "mcb3_dram_dq[13]"                          LOC = "U1" ;
NET  "mcb3_dram_dq[14]"                          LOC = "V2" ;
NET  "mcb3_dram_dq[15]"                          LOC = "V1" ;
NET  "mcb3_dram_dq[1]"                           LOC = "N1" ;
NET  "mcb3_dram_dq[2]"                           LOC = "M2" ;
NET  "mcb3_dram_dq[3]"                           LOC = "M1" ;
NET  "mcb3_dram_dq[4]"                           LOC = "J3" ;
NET  "mcb3_dram_dq[5]"                           LOC = "J1" ;
NET  "mcb3_dram_dq[6]"                           LOC = "K2" ;
NET  "mcb3_dram_dq[7]"                           LOC = "K1" ;
NET  "mcb3_dram_dq[8]"                           LOC = "P2" ;
NET  "mcb3_dram_dq[9]"                           LOC = "P1" ;
NET  "mcb3_dram_dqs"                             LOC = "L3" ;
NET  "mcb3_dram_dqs_n"                           LOC = "L1" ;
#NET  "mcb3_dram_odt"                             LOC = "M3" ;
NET  "mcb3_dram_ras_n"                           LOC = "N4" ;
NET  "mcb3_dram_udm"                             LOC = "H2" ;
NET  "mcb3_dram_udqs"                            LOC = "T2" ;
NET  "mcb3_dram_udqs_n"                          LOC = "T1" ;
NET  "mcb3_dram_we_n"                            LOC = "D2" ;

# The following pins are available for used as RZQ or ZIO pins#
NET  "mcb3_rzq"                                  LOC = "AA2" ;
NET  "mcb3_zio"                                  LOC = "Y2" ;