Subversion Repositories usb_fpga_2_13

# NET "CLK" TNM_NET = "CLK";
# TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
# NET "CLK"  LOC = "P52" | IOSTANDARD = LVCMOS33 ;

NET "IFCLK" TNM_NET = "IFCLK";
TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20 ns HIGH 50 %;
NET "IFCLK"  LOC = "P56" | IOSTANDARD = LVCMOS33 ;

# TIMESPEC "TS_CLK_IFCLK" = FROM "CLK" TO "IFCLK" 3ns DATAPATHONLY;
# TIMESPEC "TS_IFCLK_CLK" = FROM "IFCLK" TO "CLK" 3ns DATAPATHONLY;

NET "RESET" LOC = "P31" | IOSTANDARD = LVCMOS33 ;                       # PA0
NET "SLOE"  LOC = "P30" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;          # PA2
NET "CONT"  LOC = "P28" | IOSTANDARD = LVCMOS33 ;                       # PA3
NET "FIFOADR0"  LOC = "P27" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;      # PA4
NET "FIFOADR1"  LOC = "P26" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;      # PA5
NET "PKTEND"  LOC = "P25" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;        # PA6
# NET "PA7"  LOC = "P24" | IOSTANDARD = LVCMOS33 ;

NET "FD<0>"  LOC = "P65" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<1>"  LOC = "P63" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<2>"  LOC = "P60" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<3>"  LOC = "P59" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<4>"  LOC = "P51" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<5>"  LOC = "P50" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<6>"  LOC = "P47" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<7>"  LOC = "P46" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<8>"  LOC = "P21" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<9>"  LOC = "P20" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<10>"  LOC = "P18" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<11>"  LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<12>"  LOC = "P15" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<13>"  LOC = "P14" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<14>"  LOC = "P13" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "FD<15>"  LOC = "P12" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;

NET "FLAGB"  LOC = "P55" | IOSTANDARD = LVCMOS33 ;

NET "SLRD"  LOC = "P11" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "SLWR"  LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;