URL
https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
Subversion Repositories usb_fpga_2_14
[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.16/] [memfifo.xdc] - Rev 2
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# IFCLKcreate_clock -name ifclk_in -period 20.833 [get_ports ifclk_in]set_property PACKAGE_PIN J19 [get_ports ifclk_in]set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in]# GPIOset_property PACKAGE_PIN M22 [get_ports {gpio_clk}] ;# PA0/INT0#set_property PACKAGE_PIN M21 [get_ports {gpio_dir}] ;# PA1/INT1#set_property PACKAGE_PIN M18 [get_ports {gpio_dat}] ;# PA3/WU2set_property PULLUP true [get_ports {gpio_dat}]set_property IOSTANDARD LVCMOS33 [get_ports {gpio_*}]# resetset_property PACKAGE_PIN R18 [get_ports {reset}] ;# PA7/FLAGD/SLCS#set_property IOSTANDARD LVCMOS33 [get_ports {reset}]# SW8set_property PACKAGE_PIN D17 [get_ports {SW8}] ;# B11 / D17~IO_L12P_T1_MRCC_16set_property IOSTANDARD LVCMOS33 [get_ports {SW8}]set_property PULLUP true [get_ports {SW8}]# led1set_property PACKAGE_PIN B21 [get_ports {led1[0]}] ;# A6 / B21~IO_L21P_T3_DQS_16set_property PACKAGE_PIN A21 [get_ports {led1[1]}] ;# B6 / A21~IO_L21N_T3_DQS_16set_property PACKAGE_PIN D20 [get_ports {led1[2]}] ;# A7 / D20~IO_L19P_T3_16set_property PACKAGE_PIN C20 [get_ports {led1[3]}] ;# B7 / C20~IO_L19N_T3_VREF_16set_property PACKAGE_PIN B20 [get_ports {led1[4]}] ;# A8 / B20~IO_L16P_T2_16set_property PACKAGE_PIN A20 [get_ports {led1[5]}] ;# B8 / A20~IO_L16N_T2_16set_property PACKAGE_PIN C19 [get_ports {led1[6]}] ;# A9 / C19~IO_L13N_T2_MRCC_16set_property PACKAGE_PIN A19 [get_ports {led1[7]}] ;# B9 / A19~IO_L17N_T2_16set_property PACKAGE_PIN C18 [get_ports {led1[8]}] ;# A10 / C18~IO_L13P_T2_MRCC_16set_property PACKAGE_PIN A18 [get_ports {led1[9]}] ;# B10 / A18~IO_L17P_T2_16set_property IOSTANDARD LVCMOS33 [get_ports {led1[*]}]set_property DRIVE 12 [get_ports {led1[*]}]# FDset_property PACKAGE_PIN P20 [get_ports {fd[0]}] ;# PB0/FD0set_property PACKAGE_PIN N17 [get_ports {fd[1]}] ;# PB1/FD1set_property PACKAGE_PIN P21 [get_ports {fd[2]}] ;# PB2/FD2set_property PACKAGE_PIN R21 [get_ports {fd[3]}] ;# PB3/FD3set_property PACKAGE_PIN T21 [get_ports {fd[4]}] ;# PB4/FD4set_property PACKAGE_PIN U21 [get_ports {fd[5]}] ;# PB5/FD5set_property PACKAGE_PIN P19 [get_ports {fd[6]}] ;# PB6/FD6set_property PACKAGE_PIN R19 [get_ports {fd[7]}] ;# PB7/FD7set_property PACKAGE_PIN T20 [get_ports {fd[8]}] ;# PD0/FD8set_property PACKAGE_PIN U20 [get_ports {fd[9]}] ;# PD1/FD9set_property PACKAGE_PIN U18 [get_ports {fd[10]}] ;# PD2/FD10set_property PACKAGE_PIN U17 [get_ports {fd[11]}] ;# PD3/FD11set_property PACKAGE_PIN W19 [get_ports {fd[12]}] ;# PD4/FD12set_property PACKAGE_PIN W20 [get_ports {fd[13]}] ;# PD5/FD13set_property PACKAGE_PIN W21 [get_ports {fd[14]}] ;# PD6/FD14set_property PACKAGE_PIN W22 [get_ports {fd[15]}] ;# PD7/FD15set_property IOSTANDARD LVCMOS33 [get_ports {fd[*]}]# SLRDset_property PACKAGE_PIN AB22 [get_ports {SLRD}] ;# RDY0/SLRDset_property IOSTANDARD LVCMOS33 [get_ports {SLRD}]# SLWRset_property PACKAGE_PIN AB21 [get_ports {SLWR}] ;# RDY1/SLWRset_property IOSTANDARD LVCMOS33 [get_ports {SLWR}]# FLAGAset_property PACKAGE_PIN K19 [get_ports {FLAGA}] ;# CTL0/FLAGAset_property IOSTANDARD LVCMOS33 [get_ports {FLAGA}]# FLAGBset_property PACKAGE_PIN K18 [get_ports {FLAGB}] ;# CTL1/FLAGBset_property IOSTANDARD LVCMOS33 [get_ports {FLAGB}]# SLOEset_property PACKAGE_PIN M20 [get_ports {SLOE}] ;# PA2/SLOEset_property IOSTANDARD LVCMOS33 [get_ports {SLOE}]# FIFOADDR0set_property PACKAGE_PIN N19 [get_ports {FIFOADDR0} ] ;# PA4/FIFOADR0set_property IOSTANDARD LVCMOS33 [get_ports {FIFOADDR0} ]# FIFOADDR1set_property PACKAGE_PIN N18 [get_ports {FIFOADDR1}] ;# PA5/FIFOADR1set_property IOSTANDARD LVCMOS33 [get_ports {FIFOADDR1}]# PKTENDset_property PACKAGE_PIN P17 [get_ports {PKTEND}] ;# PA6/PKTENDset_property IOSTANDARD LVCMOS33 [get_ports {PKTEND}]# bitstream settings for all ZTEX Series 2 FPGA Boardsset_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]set_property BITSTREAM.GENERAL.COMPRESS true [current_design]