Subversion Repositories usb_fpga_2_16

memfifo
-------
This example demonstrates:

* High speed EZ-USB -> FPGA transfers using the Slave FIFO interface
* High speed FPGA -> EZ-USB transfers using the Slave FIFO interface
* Usage of the DDR3 SDRAM

All SDRAM is used to build a large FIFO. Input of this FIFO is either
USB Endpoint 6 through the Slave FIFO interface of EZ-USB or a test
pattern generator with variable data rate. Data is written to PC 
using Enpdoint 2.

The host software writes the data (in EP6 input mode), reads it back
and verifies it. Several tests are performed in order to test flow 
control, data rates, etc.

The HDL sources contain 3 modules:
1. ezusb_io.v: Implements the EZ-USB Slave FIFO interface for both 
    directions. It also includes an scheduler (required if both
    directions are used at the same time) and short packets (PKTEND).
2. dram_fifo.v: Implements a huge FIFO  from all SDRAM.
3. memfifo.c: The top level module glues everything together.

ezusb_io and dram_fifo are re-usable for many other projects.

PIN PA7 is the reset input.

Data source source is  is selected by PA1:PA0:
PA1:PA0  Source 
----------------------
0:0      USB Endpoint 6 (EZ-USB Slave FIFO interface)
0:1      48 MByte/s test pattern generator
1:0      12 MByte/s test pattern generator
1:1      Test pattern generator, speed selected by SW8 of the debug board

Debug Board (not required)
--------------------------
LED1: Debug/status output, see SW10
LED2-3: Fill level of the DRAM FIFO
SW8: Speed of test pattern generator in source mode 11
     on: 12 MByte/s
     off: 48 MByte/s
SW10 on: status signals from dram_fifo module
     off:status signals from top level module