Subversion Repositories usimplez

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 11:43:31 2011 " "Info: Processing started: Wed Nov 09 11:43:31 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=on --write_settings_files=off usimplez -c usimplez_top " "Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off usimplez -c usimplez_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "usimplez_top EP2S15F484C3 " "Info: Automatically selected device EP2S15F484C3 for design usimplez_top" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." {  } {  } 0 0 "Feature %1!s! is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" {  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ E13 " "Info: Pin ~DATA0~ is reserved at location E13" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { ~DATA0~ } } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez00/" 0 { } { { 0 { 0 ""} 0 474 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 7 " "Critical Warning: No exact pin location assignment(s) for 7 pins of 7 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "we_o " "Info: Pin we_o not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { we_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 61 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { we_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez00/" 0 { } { { 0 { 0 ""} 0 81 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "in0_o " "Info: Pin in0_o not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { in0_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 62 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { in0_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez00/" 0 { } { { 0 { 0 ""} 0 82 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "in1_o " "Info: Pin in1_o not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { in1_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 63 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { in1_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez00/" 0 { } { { 0 { 0 ""} 0 83 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "op0_o " "Info: Pin op0_o not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { op0_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 64 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { op0_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez00/" 0 { } { { 0 { 0 ""} 0 84 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "op1_o " "Info: Pin op1_o not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { op1_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 65 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { op1_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez00/" 0 { } { { 0 { 0 ""} 0 85 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_i " "Info: Pin clk_i not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez00/" 0 { } { { 0 { 0 ""} 0 79 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rst_i " "Info: Pin rst_i not assigned to an exact location on the device" {  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 60 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez00/" 0 { } { { 0 { 0 ""} 0 80 3016 4149 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_i (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk_i (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez00/" 0 { } { { 0 { 0 ""} 0 79 3016 4149 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1}  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "6 unused 3.3V 1 5 0 " "Info: Number of I/O pins in group: 6 (unused VREF, 3.3V VCCIO, 1 input, 5 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 39 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  39 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 44 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  44 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 49 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  49 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 35 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  35 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 44 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  44 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 40 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 34 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  34 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use undetermined 0 6 " "Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.534 ns memory register " "Info: Estimated most critical path is memory to register delay of 3.534 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a3~porta_address_reg8 1 MEM M4K_X20_Y14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X20_Y14; Fanout = 1; MEM Node = 'usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a3~porta_address_reg8'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 } "NODE_NAME" } } { "db/altsyncram_k961.tdf" "" { Text "C:/Altera/qdesigns/usimplez00/db/altsyncram_k961.tdf" 96 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.793 ns) 1.793 ns usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a3 2 MEM M4K_X20_Y14 4 " "Info: 2: + IC(0.000 ns) + CELL(1.793 ns) = 1.793 ns; Loc. = M4K_X20_Y14; Fanout = 4; MEM Node = 'usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a3'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.793 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3 } "NODE_NAME" } } { "db/altsyncram_k961.tdf" "" { Text "C:/Altera/qdesigns/usimplez00/db/altsyncram_k961.tdf" 96 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.863 ns) + CELL(0.350 ns) 3.006 ns usimplez_cpu:cpu\|Add2~15 3 COMB LAB_X30_Y14 2 " "Info: 3: + IC(0.863 ns) + CELL(0.350 ns) = 3.006 ns; Loc. = LAB_X30_Y14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~15'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.213 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3 usimplez_cpu:cpu|Add2~15 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.041 ns usimplez_cpu:cpu\|Add2~19 4 COMB LAB_X30_Y14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 3.041 ns; Loc. = LAB_X30_Y14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~19'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~15 usimplez_cpu:cpu|Add2~19 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.076 ns usimplez_cpu:cpu\|Add2~23 5 COMB LAB_X30_Y14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 3.076 ns; Loc. = LAB_X30_Y14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~23'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~19 usimplez_cpu:cpu|Add2~23 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.111 ns usimplez_cpu:cpu\|Add2~27 6 COMB LAB_X30_Y14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 3.111 ns; Loc. = LAB_X30_Y14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~27'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~23 usimplez_cpu:cpu|Add2~27 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.146 ns usimplez_cpu:cpu\|Add2~31 7 COMB LAB_X30_Y14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 3.146 ns; Loc. = LAB_X30_Y14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~31'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~27 usimplez_cpu:cpu|Add2~31 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.061 ns) + CELL(0.035 ns) 3.242 ns usimplez_cpu:cpu\|Add2~35 8 COMB LAB_X30_Y14 2 " "Info: 8: + IC(0.061 ns) + CELL(0.035 ns) = 3.242 ns; Loc. = LAB_X30_Y14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~35'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { usimplez_cpu:cpu|Add2~31 usimplez_cpu:cpu|Add2~35 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.277 ns usimplez_cpu:cpu\|Add2~39 9 COMB LAB_X30_Y14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.035 ns) = 3.277 ns; Loc. = LAB_X30_Y14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~39'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~35 usimplez_cpu:cpu|Add2~39 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.312 ns usimplez_cpu:cpu\|Add2~43 10 COMB LAB_X30_Y14 1 " "Info: 10: + IC(0.000 ns) + CELL(0.035 ns) = 3.312 ns; Loc. = LAB_X30_Y14; Fanout = 1; COMB Node = 'usimplez_cpu:cpu\|Add2~43'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~39 usimplez_cpu:cpu|Add2~43 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 3.437 ns usimplez_cpu:cpu\|Add2~46 11 COMB LAB_X30_Y14 1 " "Info: 11: + IC(0.000 ns) + CELL(0.125 ns) = 3.437 ns; Loc. = LAB_X30_Y14; Fanout = 1; COMB Node = 'usimplez_cpu:cpu\|Add2~46'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { usimplez_cpu:cpu|Add2~43 usimplez_cpu:cpu|Add2~46 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(-0.058 ns) + CELL(0.155 ns) 3.534 ns usimplez_cpu:cpu\|ac_reg_s\[11\] 12 REG LAB_X30_Y14 3 " "Info: 12: + IC(-0.058 ns) + CELL(0.155 ns) = 3.534 ns; Loc. = LAB_X30_Y14; Fanout = 3; REG Node = 'usimplez_cpu:cpu\|ac_reg_s\[11\]'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.097 ns" { usimplez_cpu:cpu|Add2~46 usimplez_cpu:cpu|ac_reg_s[11] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.668 ns ( 75.50 % ) " "Info: Total cell delay = 2.668 ns ( 75.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.866 ns ( 24.50 % ) " "Info: Total interconnect delay = 0.866 ns ( 24.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.534 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3 usimplez_cpu:cpu|Add2~15 usimplez_cpu:cpu|Add2~19 usimplez_cpu:cpu|Add2~23 usimplez_cpu:cpu|Add2~27 usimplez_cpu:cpu|Add2~31 usimplez_cpu:cpu|Add2~35 usimplez_cpu:cpu|Add2~39 usimplez_cpu:cpu|Add2~43 usimplez_cpu:cpu|Add2~46 usimplez_cpu:cpu|ac_reg_s[11] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X13_Y14 X26_Y27 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X13_Y14 to location X26_Y27" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "we_o 0 " "Info: Pin \"we_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "in0_o 0 " "Info: Pin \"in0_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "in1_o 0 " "Info: Pin \"in1_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "op0_o 0 " "Info: Pin \"op0_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "op1_o 0 " "Info: Pin \"op1_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "236 " "Info: Peak virtual memory: 236 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 11:43:53 2011 " "Info: Processing ended: Wed Nov 09 11:43:53 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Info: Elapsed time: 00:00:22" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Info: Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}