Subversion Repositories wb_lcd

// File: wb_lcd.v
// Generated by MyHDL 0.6
// Date: Mon Apr 20 03:13:34 2009
 
`timescale 1ns/10ps
 
module wb_lcd (
    wb_clk_i,
    wb_rst_i,
    wb_dat_i,
    wb_dat_o,
    wb_adr_i,
    wb_sel_i,
    wb_we_i,
    wb_cyc_i,
    wb_stb_i,
    wb_ack_o,
    SF_D,
    LCD_E,
    LCD_RS,
    LCD_RW
);
 
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
reg [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
reg wb_ack_o;
output [3:0] SF_D;
reg [3:0] SF_D;
output LCD_E;
reg LCD_E;
output LCD_RS;
wire LCD_RS;
output LCD_RW;
wire LCD_RW;
 
wire busy;
reg lcd_we;
wire mylcd_tx_init;
wire mylcd_delay_load;
reg mylcd_tx_done;
reg [3:0] mylcd_SF_D1;
reg [3:0] mylcd_SF_D0;
reg mylcd_LCD_E1;
reg mylcd_LCD_E0;
wire mylcd_delay_done;
reg [7:0] mylcd_tx_byte;
reg [6:0] mylcd_wr_addr;
wire mylcd_output_selector;
reg [4:0] mylcd_state;
reg [19:0] mylcd_tx_delay_value;
reg [19:0] mylcd_main_delay_value;
reg mylcd_tx_delay_load;
reg [19:0] mylcd_delay_value;
reg [6:0] mylcd_wr_dat;
reg mylcd_main_delay_load;
reg [2:0] mylcd_tx_state;
reg [20:0] mylcd_counter_counter;
 
 
 
always @(busy, wb_we_i, wb_stb_i, wb_cyc_i, wb_adr_i) begin: WB_LCD_WISHBONE_LOGIC
    wb_ack_o <= (wb_cyc_i & wb_stb_i);
 
    lcd_we <= (wb_cyc_i & wb_stb_i & wb_we_i & (wb_adr_i != 128));
    if (busy) begin
        wb_dat_o <= 1;
    end
    else begin
        wb_dat_o <= 0;
    end
end
 
 
assign mylcd_output_selector = ((mylcd_state == 5'b00000) | (mylcd_state == 5'b00001) | (mylcd_state == 5'b00010) | (mylcd_state == 5'b00011) | (mylcd_state == 5'b00100) | (mylcd_state == 5'b00101) | (mylcd_state == 5'b00110) | (mylcd_state == 5'b00111) | (mylcd_state == 5'b01000) | (mylcd_state == 5'b01001));
 
always @(mylcd_main_delay_value, mylcd_tx_delay_load, mylcd_tx_delay_value) begin: WB_LCD_MYLCD_CONUNTER_SHARING_VALUE
    if (mylcd_tx_delay_load) begin
        mylcd_delay_value <= mylcd_tx_delay_value;
    end
    else begin
        mylcd_delay_value <= mylcd_main_delay_value;
    end
end
 
always @(posedge wb_clk_i, posedge wb_rst_i) begin: WB_LCD_MYLCD_DISPLAYFSM
    if ((wb_rst_i == 1)) begin
        mylcd_state <= 5'b00000;
        mylcd_main_delay_load <= 0;
        mylcd_main_delay_value <= 0;
        mylcd_SF_D1 <= 0;
        mylcd_LCD_E1 <= 0;
        mylcd_tx_byte <= 0;
    end
    else begin
        mylcd_main_delay_load <= 0;
 
        mylcd_main_delay_value <= 0;
 
        // synthesis parallel_case full_case
        casez (mylcd_state)
            5'b00000: begin
                mylcd_tx_byte <= 0;
                mylcd_state <= 5'b00001;
                mylcd_main_delay_load <= 1;
                mylcd_main_delay_value <= 750000;
            end
            5'b00001: begin
                mylcd_main_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00010;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 11;
                end
            end
            5'b00010: begin
                mylcd_main_delay_load <= 0;
                mylcd_SF_D1 <= 3;
                mylcd_LCD_E1 <= 1;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00011;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 205000;
                end
            end
            5'b00011: begin
                mylcd_main_delay_load <= 0;
                mylcd_LCD_E1 <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00100;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 11;
                end
            end
            5'b00100: begin
                mylcd_main_delay_load <= 0;
                mylcd_SF_D1 <= 3;
                mylcd_LCD_E1 <= 1;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00101;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 5000;
                end
            end
            5'b00101: begin
                mylcd_main_delay_load <= 0;
                mylcd_LCD_E1 <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00110;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 11;
                end
            end
            5'b00110: begin
                mylcd_main_delay_load <= 0;
                mylcd_SF_D1 <= 3;
                mylcd_LCD_E1 <= 1;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b00111;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 2000;
                end
            end
            5'b00111: begin
                mylcd_main_delay_load <= 0;
                mylcd_LCD_E1 <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b01000;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 11;
                end
            end
            5'b01000: begin
                mylcd_main_delay_load <= 0;
                mylcd_SF_D1 <= 2;
                mylcd_LCD_E1 <= 1;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b01001;
 
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 2000;
                end
            end
            5'b01001: begin
                mylcd_main_delay_load <= 0;
                mylcd_LCD_E1 <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b01010;
 
                end
            end
            5'b01010: begin
                mylcd_tx_byte <= 40;
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b01011;
                end
            end
            5'b01011: begin
                mylcd_tx_byte <= 6;
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b01100;
                end
            end
            5'b01100: begin
                mylcd_tx_byte <= 12;
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b01101;
                end
            end
            5'b01101: begin
                mylcd_tx_byte <= 1;
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b01111;
                    mylcd_main_delay_load <= 1;
                    mylcd_main_delay_value <= 82000;
                end
            end
            5'b01110: begin
                mylcd_state <= 5'b01111;
            end
            5'b01111: begin
                mylcd_tx_byte <= 0;
                if (mylcd_delay_done) begin
                    mylcd_state <= 5'b10000;
 
                end
            end
            5'b10000: begin
                mylcd_tx_byte <= 0;
                if (lcd_we) begin
                    mylcd_state <= 5'b10001;
                    mylcd_wr_addr <= wb_adr_i;
                    mylcd_wr_dat <= wb_dat_i;
                end
                else begin
                    mylcd_state <= 5'b10000;
                end
            end
            5'b10001: begin
                mylcd_tx_byte <= (128 | mylcd_wr_addr);
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b10010;
                end
            end
            5'b10010: begin
                mylcd_tx_byte <= mylcd_wr_dat;
                if (mylcd_tx_done) begin
                    mylcd_state <= 5'b10000;
 
                end
            end
        endcase
    end
end
 
always @(posedge wb_clk_i, posedge wb_rst_i) begin: WB_LCD_MYLCD_TXFSM
    if ((wb_rst_i == 1)) begin
        mylcd_tx_state <= 3'b110;
        mylcd_SF_D0 <= 0;
        mylcd_LCD_E0 <= 0;
    end
    else begin
        mylcd_tx_delay_load <= 0;
 
        mylcd_tx_delay_value <= 0;
 
        // synthesis parallel_case full_case
        casez (mylcd_tx_state)
            3'b000: begin
                mylcd_LCD_E0 <= 0;
                mylcd_SF_D0 <= mylcd_tx_byte[8-1:4];
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b001;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 12;
                end
            end
            3'b001: begin
                mylcd_LCD_E0 <= 1;
                mylcd_SF_D0 <= mylcd_tx_byte[8-1:4];
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b010;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 50;
                end
            end
            3'b010: begin
                mylcd_LCD_E0 <= 0;
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b011;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 2;
                end
            end
            3'b011: begin
                mylcd_LCD_E0 <= 0;
                mylcd_SF_D0 <= mylcd_tx_byte[4-1:0];
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b100;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 12;
                end
            end
            3'b100: begin
                mylcd_LCD_E0 <= 1;
                mylcd_SF_D0 <= mylcd_tx_byte[4-1:0];
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b101;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 2000;
                end
            end
            3'b101: begin
                mylcd_LCD_E0 <= 0;
                mylcd_tx_delay_load <= 0;
                if (mylcd_delay_done) begin
                    mylcd_tx_state <= 3'b110;
                    mylcd_tx_done <= 1;
                end
            end
            3'b110: begin
                mylcd_LCD_E0 <= 0;
                mylcd_tx_done <= 0;
                mylcd_tx_delay_load <= 0;
                if (mylcd_tx_init) begin
                    mylcd_tx_state <= 3'b000;
                    mylcd_tx_delay_load <= 1;
                    mylcd_tx_delay_value <= 2;
                end
            end
        endcase
    end
end
 
 
assign mylcd_delay_load = (mylcd_tx_delay_load || mylcd_main_delay_load);
 
 
assign busy = (mylcd_state != 5'b10000);
assign LCD_RW = 0;
 
always @(mylcd_SF_D1, mylcd_SF_D0, mylcd_LCD_E1, mylcd_LCD_E0, mylcd_output_selector) begin: WB_LCD_MYLCD_OUTPUT_TX_OR_INIT_MUX
    if (mylcd_output_selector) begin
        SF_D <= mylcd_SF_D1;
        LCD_E <= mylcd_LCD_E1;
    end
    else begin
        SF_D <= mylcd_SF_D0;
        LCD_E <= mylcd_LCD_E0;
    end
end
 
 
assign mylcd_tx_init = ((~mylcd_tx_done) & ((mylcd_state == 5'b01010) | (mylcd_state == 5'b01011) | (mylcd_state == 5'b01100) | (mylcd_state == 5'b01101) | (mylcd_state == 5'b10001) | (mylcd_state == 5'b10010)));
assign LCD_RS = (~(((mylcd_state == 5'b01010) != 0) | (mylcd_state == 5'b01011) | (mylcd_state == 5'b01100) | (mylcd_state == 5'b01101) | (mylcd_state == 5'b10001)));
 
 
assign mylcd_delay_done = (mylcd_counter_counter == 0);
 
always @(posedge wb_clk_i) begin: WB_LCD_MYLCD_COUNTER_COUNTDOWN_LOGIC
    if (mylcd_delay_load) begin
        mylcd_counter_counter <= mylcd_delay_value;
    end
    else begin
        mylcd_counter_counter <= (mylcd_counter_counter - 1);
    end
end
 
endmodule