URL
https://opencores.org/ocsvn/wiegand_ctl/wiegand_ctl/trunk
Subversion Repositories wiegand_ctl
[/] [wiegand_ctl/] [trunk/] [syn/] [xilinx/] [wiegand_tx/] [ise/] [wiegand_tx_top/] [iseconfig/] [wiegand_tx_top.projectmgr] - Rev 17
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<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="wiegand_tx_top" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/Automatic `includes</ClosedNode>
<ClosedNode>/wiegand_tx_top C:|Users|jeffA|Desktop|rtl|wiegand|trunk|rtl|verilog|wiegand_tx_top.v</ClosedNode>
</ClosedNodes>
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<SelectedItem>wiegand_tx_top (C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v)</SelectedItem>
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<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>wiegand_tx_top (C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
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<ClosedNode>Design Utilities</ClosedNode>
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<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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<CurrentItem>fifos.v</CurrentItem>
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<ItemView guiview="Library" >
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<ClosedNode>work</ClosedNode>
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<CurrentItem>work</CurrentItem>
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Implement Design</SelectedItem>
</SelectedItems>
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<CurrentItem>Implement Design</CurrentItem>
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</Project>