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[/] [xucpu/] [trunk/] [dev/] [bus/] [main.vhdl] - Rev 41

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-- Copyright 2015, Jürgen Defurne
--
-- This file is part of the Experimental Unstable CPU System.
--
-- The Experimental Unstable CPU System Is free software: you can redistribute
-- it and/or modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- The Experimental Unstable CPU System is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
-- General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with Experimental Unstable CPU System. If not, see
-- http://www.gnu.org/licenses/lgpl.txt.
 
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.components.ALL;
USE work.ram_parts.ALL;
USE work.mux_parts.ALL;
USE work.controllers.ALL;
 
-- LIBRARY unisim;
-- USE unisim.vcomponents.ALL;
 
ENTITY system IS
  PORT (
    clock     : IN  STD_LOGIC;
    reset     : IN  STD_LOGIC;
    led_out   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    switch_in : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    pushb_in  : IN  STD_LOGIC_VECTOR(4 DOWNTO 0));
END system;
 
ARCHITECTURE Structural OF system IS
 
END Structural;
 

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