Subversion Repositories xucpu

NET "CLOCK" LOC = L15;
NET "reset" LOC = T15;

NET "led_out[0]" LOC = U18;
NET "led_out[1]" LOC = M14;
NET "led_out[2]" LOC = N14;
NET "led_out[3]" LOC = L14;
NET "led_out[4]" LOC = M13;
NET "led_out[5]" LOC = D4;
NET "led_out[6]" LOC = P16;
NET "led_out[7]" LOC = N12;
NET "pushb_in[0]" LOC = N4;
NET "pushb_in[1]" LOC = F5;
NET "pushb_in[2]" LOC = F6;
NET "pushb_in[3]" LOC = P4;
NET "pushb_in[4]" LOC = P3;
NET "switch_in[0]" LOC = A10;
NET "switch_in[1]" LOC = D14;
NET "switch_in[2]" LOC = C14;
NET "switch_in[3]" LOC = P15;
NET "switch_in[4]" LOC = P12;
NET "switch_in[5]" LOC = R5;
NET "switch_in[6]" LOC = T5;
NET "switch_in[7]" LOC = E4;
#Created by Constraints Editor (xc6slx45-csg324-2) - 2014/12/21
NET "clock" TNM_NET = "clock";
TIMESPEC TS_clock = PERIOD "clock" 10 ns HIGH 50 %;
INST "pushb_in[0]" TNM = "Simple_IO";
INST "pushb_in[1]" TNM = "Simple_IO";
INST "pushb_in[2]" TNM = "Simple_IO";
INST "pushb_in[3]" TNM = "Simple_IO";
INST "pushb_in[4]" TNM = "Simple_IO";
INST "switch_in[0]" TNM = "Simple_IO";
INST "switch_in[1]" TNM = "Simple_IO";
INST "switch_in[2]" TNM = "Simple_IO";
INST "switch_in[3]" TNM = "Simple_IO";
INST "switch_in[4]" TNM = "Simple_IO";
INST "switch_in[5]" TNM = "Simple_IO";
INST "switch_in[6]" TNM = "Simple_IO";
INST "switch_in[7]" TNM = "Simple_IO";
#Created by Constraints Editor (xc6slx45-csg324-2) - 2014/12/21
TIMEGRP "Simple_IO" OFFSET = IN 100 ns VALID 100 ns BEFORE "clock" RISING;
INST "led_out[0]" TNM = "Simple_output";
INST "led_out[1]" TNM = "Simple_output";
INST "led_out[2]" TNM = "Simple_output";
INST "led_out[3]" TNM = "Simple_output";
INST "led_out[4]" TNM = "Simple_output";
INST "led_out[5]" TNM = "Simple_output";
INST "led_out[6]" TNM = "Simple_output";
INST "led_out[7]" TNM = "Simple_output";
TIMEGRP "Simple_output" OFFSET = OUT 100 ns AFTER "clock";
#Created by Constraints Editor (xc6slx45-csg324-2) - 2014/12/21
INST "CTRL1/OPERATION_0" TNM = "TS_datapath";
INST "CTRL1/OPERATION_1" TNM = "TS_datapath";
INST "CTRL1/OPERATION_2" TNM = "TS_datapath";
INST "CTRL1/OPERATION_3" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_A_0" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_A_1" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_A_2" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_A_3" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_B_0" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_B_1" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_B_2" TNM = "TS_datapath";
INST "CTRL1/REG_ADDR_B_3" TNM = "TS_datapath";
INST "MEM1/Mram_mem1" TNM = "TS_ram";
#Created by Constraints Editor (xc6slx45-csg324-2) - 2014/12/21
TIMESPEC TS_reset = FROM "Time_RST" TO "TS_ram" TIG ;
#Created by Constraints Editor (xc6slx45-csg324-2) - 2014/12/21
INST "PC/Q_0" TNM = "Time_PC";
INST "PC/Q_1" TNM = "Time_PC";
INST "PC/Q_2" TNM = "Time_PC";
INST "PC/Q_3" TNM = "Time_PC";
INST "PC/Q_4" TNM = "Time_PC";
INST "PC/Q_5" TNM = "Time_PC";
INST "PC/Q_6" TNM = "Time_PC";
INST "PC/Q_7" TNM = "Time_PC";
INST "PC/Q_8" TNM = "Time_PC";
INST "PC/Q_9" TNM = "Time_PC";
INST "PC/Q_10" TNM = "Time_PC";
INST "PC/Q_11" TNM = "Time_PC";
INST "PC/Q_12" TNM = "Time_PC";
INST "PC/Q_13" TNM = "Time_PC";
INST "PC/Q_14" TNM = "Time_PC";
TIMESPEC TS_PC_TIG = FROM "Time_RST" TO "Time_PC" TIG ;