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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [CII_Starter_USB_API.fit.rpt] - Rev 12
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Fitter report for CII_Starter_USB_APISun Oct 11 12:24:59 2009Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. Fitter Netlist Optimizations5. Fitter Automatic Asynchronous Signal Pipelining Statistics6. Pin-Out File7. Fitter Resource Usage Summary8. Input Pins9. Output Pins10. Bidir Pins11. I/O Bank Usage12. All Package Pins13. PLL Summary14. PLL Usage15. Output Pin Default Load For Reported TCO16. Fitter Resource Utilization by Entity17. Delay Chain Summary18. Pad To Core Delay Chain Fanout19. Control Signals20. Global & Other Fast Signals21. Non-Global High Fan-Out Signals22. Fitter RAM Summary23. Interconnect Usage Summary24. LAB Logic Elements25. LAB-wide Signals26. LAB Signals Sourced27. LAB Signals Sourced Out28. LAB Distinct Inputs29. Fitter Device Options30. Operating Settings and Conditions31. Estimated Delay Added for Hold Timing32. Advanced Data - General33. Advanced Data - Placement Preparation34. Advanced Data - Placement35. Advanced Data - Routing36. Fitter Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2009 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-----------------------------------------------------------------------------------+; Fitter Summary ;+------------------------------------+----------------------------------------------+; Fitter Status ; Successful - Sun Oct 11 12:24:59 2009 ;; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;; Revision Name ; CII_Starter_USB_API ;; Top-level Entity Name ; CII_Starter_USB_API ;; Family ; Cyclone II ;; Device ; EP2C20F484C7 ;; Timing Models ; Final ;; Total logic elements ; 2,242 / 18,752 ( 12 % ) ;; Total combinational functions ; 1,995 / 18,752 ( 11 % ) ;; Dedicated logic registers ; 1,092 / 18,752 ( 6 % ) ;; Total registers ; 1093 ;; Total pins ; 283 / 315 ( 90 % ) ;; Total virtual pins ; 0 ;; Total memory bits ; 208,000 / 239,616 ( 87 % ) ;; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ;; Total PLLs ; 2 / 4 ( 50 % ) ;+------------------------------------+----------------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+--------------------------------------------------------------------+--------------------------------+--------------------------------+; Option ; Setting ; Default Value ;+--------------------------------------------------------------------+--------------------------------+--------------------------------+; Device ; EP2C20F484C7 ; ;; Use TimeQuest Timing Analyzer ; On ; Off ;; Fit Attempts to Skip ; 0 ; 0.0 ;; Perform Physical Synthesis for Combinational Logic for Performance ; On ; Off ;; Perform Register Duplication for Performance ; On ; Off ;; Perform Register Retiming for Performance ; On ; Off ;; Perform Asynchronous Signal Pipelining ; On ; Off ;; Physical Synthesis Effort Level ; Extra ; Normal ;; Use smart compilation ; Off ; Off ;; Router Timing Optimization Level ; Normal ; Normal ;; Placement Effort Multiplier ; 1.0 ; 1.0 ;; Router Effort Multiplier ; 1.0 ; 1.0 ;; Always Enable Input Buffers ; Off ; Off ;; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;; Optimize Multi-Corner Timing ; Off ; Off ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize Timing for ECOs ; Off ; Off ;; Regenerate full fit report during ECO compiles ; Off ; Off ;; Optimize IOC Register Placement for Timing ; On ; On ;; Limit to One Fitting Attempt ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; PCI I/O ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Global Memory Control Signals ; Off ; Off ;; Auto Packed Registers ; Auto ; Auto ;; Auto Delay Chains ; On ; On ;; Auto Merge PLLs ; On ; On ;; Ignore PLL Mode When Merging PLLs ; Off ; Off ;; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;; Fitter Effort ; Auto Fit ; Auto Fit ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;; Stop After Congestion Map Generation ; Off ; Off ;; Save Intermediate Fitting Results ; Off ; Off ;; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;+--------------------------------------------------------------------+--------------------------------+--------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Netlist Optimizations ;+-----------------------------------------------------------------+-------------------------------+--------------------+---------------------------------+-----------+----------------+------------------+------------------+-----------------------+; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;+-----------------------------------------------------------------+-------------------------------+--------------------+---------------------------------+-----------+----------------+------------------+------------------+-----------------------+; USB_JTAG:u1|JTAG_TRANS:u1|TDO ; Packed Register ; Register Packing ; Fast Output Register assignment ; REGOUT ; ; TDO ; DATAIN ; ;; AUDIO_DAC:u11|FLASH_Cont[0]_OTERM51 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[0]~45 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[1]_OTERM89 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[2]_OTERM87 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[3]_OTERM85 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[4]_OTERM83 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[5]_OTERM81 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[6]_OTERM79 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[7]_OTERM77 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[8]_OTERM75 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[9]_OTERM73 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[10]_OTERM71 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[11]_OTERM69 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[12]_OTERM67 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[13]_OTERM65 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[14]_OTERM63 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[15]_OTERM61 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[16]_OTERM59 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[17]_OTERM57 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[18]_OTERM55 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[19]_OTERM53 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan4~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan4~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan4~1_RESYN270_BDD271 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan4~1_RESYN352_BDD353 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan5~3 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan5~4 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan5~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan5~6_RESYN326_BDD327 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan5~6_RESYN354_BDD355 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|LessThan5~6_RESYN356_BDD357 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SIN_Cont[0]_OTERM93 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SIN_Cont[0]~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SIN_Cont[1]_NEW96_RESYN338_BDD339 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SIN_Cont[1]_OTERM97 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SIN_Cont[2]_OTERM91 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SIN_Cont[3]_OTERM95 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SIN_Cont[4]_OTERM101 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SIN_Cont[5]_OTERM99 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_X[2] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_X[3] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_X[4] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_X[5] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_X[6] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_X[7] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_X[8] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_X[9] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_Y[1] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_Y[2] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_Y[3] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_Y[4] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_Y[5] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_Y[6] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_Y[7] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_Y[8] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oCursor_Y[9] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oFL_Select[0]_OTERM103 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oFL_Select[1]_OTERM107 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|ACK2~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|ACK2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|ACK2~1_RESYN288_BDD289 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|LessThan2~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|LessThan2~0_RESYN340_BDD341 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~2_RESYN358_BDD359 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~3 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~4 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~5 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~6_RESYN278_BDD279 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~6_RESYN280_BDD281 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~6_RESYN282_BDD283 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~9 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~10 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~11 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~11_RESYN284_BDD285 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|Mux0~11_RESYN286_BDD287 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|SCLK~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|SCLK~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|SCLK~3_RESYN248_BDD249 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|SCLK~3_RESYN292_BDD293 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|SCLK~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|SCLK~4_RESYN294_BDD295 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|SD[12]~25 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|I2C_Controller:u0|SD[12]~25_RESYN336_BDD337 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|LUT_INDEX[1]~6 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|LUT_INDEX[2]~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|LUT_INDEX[2]~7_RESYN330_BDD331 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|LUT_INDEX[3]~8 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; I2C_AV_Config:u10|LUT_INDEX[3]~8_RESYN332_BDD333 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[0]_OTERM121 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[1]_OTERM105 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[2]_OTERM111 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[3]_OTERM115 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[4]_OTERM119 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[5]_OTERM109 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[6]_OTERM113 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[7]_OTERM117 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[0]~15_OTERM219 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[1]~8_OTERM205 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[2]~10_OTERM209 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[3]~12_OTERM213 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[4]~14_OTERM217 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[5]~9_OTERM207 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[6]~11_OTERM211 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[7]~13_OTERM215 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Sdram:u3|Sdram_Controller:u1|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Multi_Sdram:u3|Sdram_Controller:u1|Selector10~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~0_OTERM247 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~2_OTERM243 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~2_RTM048 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~2_RTM0245 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~2_RTM0245 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~4_OTERM239 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~4_RTM044 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~4_RTM0241 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~4_RTM0241 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~6_OTERM235 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~6_RTM040 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~6_RTM0237 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~6_RTM0237 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~8_OTERM233 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~10_OTERM231 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~12_OTERM227 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~12_RTM032 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~12_RTM0229 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~12_RTM0229 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~14_OTERM225 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~16_OTERM223 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add5~18_OTERM221 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~0_OTERM47 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~0_RTM049 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~0_RTM049 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~2_OTERM43 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~2_RTM045 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~2_RTM045 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~4_OTERM39 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~4_RTM041 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~4_RTM041 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~6_OTERM37 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~8_OTERM35 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~10_OTERM31 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~10_RTM033 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~10_RTM033 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~12_OTERM29 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~14_OTERM27 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add6~16_OTERM25 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~2_OTERM201 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~2_RTM0203 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~2_RTM0203 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~4_OTERM199 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~6_OTERM195 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~6_RTM0197 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~6_RTM0197 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~8 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~8_OTERM191 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~8_RTM0193 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~8_RTM0193 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~10_OTERM189 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~12_OTERM187 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~14_OTERM183 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~14_RTM0185 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~14_RTM0185 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~16_OTERM181 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~18_OTERM179 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~20_OTERM177 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~22_OTERM173 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~22_RTM0175 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add7~22_RTM0175 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~0_OTERM143 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~0_RTM0145 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~0_RTM0145 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~2_OTERM141 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~4_OTERM139 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~6_OTERM137 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~8 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~8_OTERM133 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~8_RTM0135 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~8_RTM0135 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~10_OTERM131 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~12_OTERM129 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~14_OTERM127 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~16_OTERM125 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add8~18_OTERM123 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~0_OTERM21 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~0_RTM023 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~0_RTM023 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~2_OTERM19 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~4_OTERM17 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~6_OTERM15 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~8_OTERM11 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~8_RTM013 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~8_RTM013 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~10_OTERM9 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~12_OTERM7 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~14_OTERM5 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~16_OTERM3 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add9~18_OTERM1 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~2_OTERM171 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~2_RTM022 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~4_OTERM169 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~6_OTERM167 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~8_OTERM165 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~10_OTERM161 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~10_RTM012 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~10_RTM0163 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~10_RTM0163 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~12_OTERM159 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~14_OTERM157 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~16_OTERM155 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~18_OTERM153 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~20_OTERM151 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~22_OTERM147 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~22_RTM0149 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Add10~22_RTM0149 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_B~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_B~21_RESYN346_BDD347 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_B~21_RESYN348_BDD349 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_B~21_RESYN350_BDD351 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_B~26 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_B~27 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_B~28 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_B~28_RESYN318_BDD319 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_B~28_RESYN320_BDD321 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_B~28_RESYN322_BDD323 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_G~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_G~23_RESYN314_BDD315 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_G~23_RESYN316_BDD317 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_R[6]~20 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_R[6]~20_RESYN250_BDD251 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_R[7]~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_R[7]~21_RESYN266_BDD267 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_R[8]~22 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Cur_Color_R[8]~22_RESYN268_BDD269 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal0~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal0~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal0~5 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal0~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal0~6_RESYN304_BDD305 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal1~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal1~1_RTM0244 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal1~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal1~2_RTM0228 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal1~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal1~3_RTM0236 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal1~3_RTM0240 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal1~4 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~3_RTM0202 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~4_RTM0184 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~4_RTM0196 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~5_RTM0192 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~6_RTM0174 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~7 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~7_RESYN260_BDD261 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal2~7_RESYN262_BDD263 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal3~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal3~5 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal3~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal3~6_RESYN342_BDD343 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal4~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal4~2_RTM0144 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal4~5 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal4~5_RTM0134 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal4~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal4~6_RESYN344_BDD345 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal5~1_RTM0162 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal5~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|Equal5~5 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~11 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~11_RTM0148 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~12_RESYN252_BDD253 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~12_RESYN298_BDD299 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~12_RESYN298_RESYN360_BDD361 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~12_RESYN298_RESYN362_BDD363 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~12_RESYN298_RESYN364_BDD365 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~12_RESYN300_BDD301 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~14 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; VGA_Controller:u8|always1~14_RESYN308_BDD309 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; mVGA_R[6]~10 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; mVGA_R[7]~11 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; mVGA_R[8]~12 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; mVIN_R[9]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; mVIN_R[9]~0_RESYN312_BDD313 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[20]_OTERM389 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|FLASH_Cont[21]_OTERM387 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SEL_Cont[0]~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SEL_Cont[1]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SEL_Cont[1]~0_OTERM381 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SEL_Cont[2]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SEL_Cont[2]~2_OTERM385 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SEL_Cont[3]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; AUDIO_DAC:u11|SEL_Cont[3]~1_OTERM383 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oPS2_TXD_Start_OTERM393 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oPS2_TXD_Start~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oSDR_TXD_Start_OTERM399 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|oSR_TXD_Start_OTERM391 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|sel_SDR_OTERM397 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|sel_SDR~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|sel_SDR~6 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; CMD_Decode:u5|sel_SR_OTERM395 ; Retimed Register ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Reset_Delay:d0|oRESET_OTERM371 ; Pipelined Asynchronous Signal ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Reset_Delay:d0|oRESET_OTERM373 ; Pipelined Asynchronous Signal ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Reset_Delay:d0|oRESET_OTERM375 ; Pipelined Asynchronous Signal ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Reset_Delay:d0|oRESET_OTERM377 ; Pipelined Asynchronous Signal ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Reset_Delay:d0|oRESET_OTERM379 ; Pipelined Asynchronous Signal ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; Reset_Delay:d0|oRESET~clkctrl ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;+-----------------------------------------------------------------+-------------------------------+--------------------+---------------------------------+-----------+----------------+------------------+------------------+-----------------------++-------------------------------------------------------------------------------------------------------------------------+; Fitter Automatic Asynchronous Signal Pipelining Statistics ;+-----------------------+-----------------+-----------------------------+-------------------------------------------------+; Asynchronous Signal ; Pipeline Stages ; Pipeline Registers Inserted ; Notes ;+-----------------------+-----------------+-----------------------------+-------------------------------------------------+; KEY[0] ; 0 ; 0 ; Asynchronous signal does not require pipelining ;; TCS~clkctrl ; 0 ; 0 ; Asynchronous signal does not require pipelining ;; Reset_Delay:d0|oRESET ; 3 ; 5 ; ;+-----------------------+-----------------+-----------------------------+-------------------------------------------------++--------------+; Pin-Out File ;+--------------+The pin-out file can be found in C:/altera/Examples/CII_Starter_demonstrations/CII_Starter_USB_API_v1/HW/CII_Starter_USB_API.pin.+--------------------------------------------------------------------------+; Fitter Resource Usage Summary ;+---------------------------------------------+----------------------------+; Resource ; Usage ;+---------------------------------------------+----------------------------+; Total logic elements ; 2,242 / 18,752 ( 12 % ) ;; -- Combinational with no register ; 1150 ;; -- Register only ; 247 ;; -- Combinational with a register ; 845 ;; ; ;; Logic element usage by number of LUT inputs ; ;; -- 4 input functions ; 1088 ;; -- 3 input functions ; 375 ;; -- <=2 input functions ; 532 ;; -- Register only ; 247 ;; ; ;; Logic elements by mode ; ;; -- normal mode ; 1642 ;; -- arithmetic mode ; 353 ;; ; ;; Total registers* ; 1,093 / 19,649 ( 6 % ) ;; -- Dedicated logic registers ; 1,092 / 18,752 ( 6 % ) ;; -- I/O registers ; 1 / 897 ( < 1 % ) ;; ; ;; Total LABs: partially or completely used ; 190 / 1,172 ( 16 % ) ;; User inserted logic elements ; 0 ;; Virtual pins ; 0 ;; I/O pins ; 283 / 315 ( 90 % ) ;; -- Clock pins ; 8 / 8 ( 100 % ) ;; Global signals ; 13 ;; M4Ks ; 51 / 52 ( 98 % ) ;; Total block memory bits ; 208,000 / 239,616 ( 87 % ) ;; Total block memory implementation bits ; 235,008 / 239,616 ( 98 % ) ;; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ;; PLLs ; 2 / 4 ( 50 % ) ;; Global clocks ; 13 / 16 ( 81 % ) ;; JTAGs ; 0 / 1 ( 0 % ) ;; ASMI blocks ; 0 / 1 ( 0 % ) ;; CRC blocks ; 0 / 1 ( 0 % ) ;; Average interconnect usage (total/H/V) ; 7% / 7% / 7% ;; Peak interconnect usage (total/H/V) ; 13% / 13% / 13% ;; Maximum fan-out node ; CLOCK_50~clkctrl ;; Maximum fan-out ; 618 ;; Highest non-global fan-out signal ; KEY[0] ;; Highest non-global fan-out ; 588 ;; Total fan-out ; 11181 ;; Average fan-out ; 3.10 ;+---------------------------------------------+----------------------------+* Register count does not include registers inside RAM blocks or DSP blocks.+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Input Pins ;+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; AUD_ADCDAT ; B6 ; 3 ; 3 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; CLOCK_24[0] ; B12 ; 4 ; 24 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; CLOCK_24[1] ; A12 ; 4 ; 24 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; CLOCK_27[0] ; D12 ; 3 ; 24 ; 27 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; CLOCK_27[1] ; E12 ; 3 ; 24 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; CLOCK_50 ; L1 ; 2 ; 0 ; 13 ; 0 ; 2 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; EXT_CLOCK ; M21 ; 6 ; 50 ; 14 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; KEY[0] ; R22 ; 6 ; 50 ; 10 ; 1 ; 588 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; KEY[1] ; R21 ; 6 ; 50 ; 10 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; KEY[2] ; T22 ; 6 ; 50 ; 9 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; KEY[3] ; T21 ; 6 ; 50 ; 9 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; PS2_CLK ; H15 ; 4 ; 44 ; 27 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; PS2_DAT ; J14 ; 4 ; 42 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; SW[0] ; L22 ; 5 ; 50 ; 14 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; SW[1] ; L21 ; 5 ; 50 ; 14 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; SW[2] ; M22 ; 6 ; 50 ; 14 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; SW[3] ; V12 ; 7 ; 26 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; SW[4] ; W12 ; 7 ; 26 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; SW[5] ; U12 ; 8 ; 26 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; SW[6] ; U11 ; 8 ; 26 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; SW[7] ; M2 ; 1 ; 0 ; 13 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; SW[8] ; M1 ; 1 ; 0 ; 13 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; SW[9] ; L2 ; 2 ; 0 ; 13 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; TCK ; C7 ; 3 ; 7 ; 27 ; 2 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; TCS ; D8 ; 3 ; 9 ; 27 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; TDI ; E8 ; 3 ; 11 ; 27 ; 3 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;; UART_RXD ; F14 ; 4 ; 35 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Output Pins ;+---------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;+---------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+; AUD_ADCLRCK ; A6 ; 3 ; 3 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; AUD_DACDAT ; B5 ; 3 ; 3 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; AUD_DACLRCK ; A5 ; 3 ; 3 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; AUD_XCK ; B4 ; 3 ; 1 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[0] ; W4 ; 1 ; 0 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[10] ; W3 ; 1 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[11] ; N6 ; 1 ; 0 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[1] ; W5 ; 1 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[2] ; Y3 ; 1 ; 0 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[3] ; Y4 ; 1 ; 0 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[4] ; R6 ; 1 ; 0 ; 7 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[5] ; R5 ; 1 ; 0 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[6] ; P6 ; 1 ; 0 ; 9 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[7] ; P5 ; 1 ; 0 ; 9 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[8] ; P3 ; 1 ; 0 ; 10 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_ADDR[9] ; N4 ; 1 ; 0 ; 10 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_BA_0 ; U3 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_BA_1 ; V4 ; 1 ; 0 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_CAS_N ; T3 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_CKE ; N3 ; 1 ; 0 ; 10 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_CLK ; U4 ; 1 ; 0 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_CS_N ; T6 ; 1 ; 0 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_LDQM ; R7 ; 1 ; 0 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_RAS_N ; T5 ; 1 ; 0 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_UDQM ; M5 ; 1 ; 0 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_WE_N ; R8 ; 1 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[0] ; AB20 ; 7 ; 48 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[10] ; R12 ; 7 ; 33 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[11] ; T12 ; 7 ; 31 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[12] ; AB14 ; 7 ; 33 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[13] ; AA13 ; 7 ; 29 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[14] ; AB13 ; 7 ; 29 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[15] ; AA12 ; 7 ; 29 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[16] ; AB12 ; 7 ; 29 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[17] ; AA20 ; 7 ; 48 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[18] ; U14 ; 7 ; 39 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[19] ; V14 ; 7 ; 37 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[1] ; AA14 ; 7 ; 33 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[20] ; U13 ; 7 ; 31 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[21] ; R13 ; 7 ; 37 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[2] ; Y16 ; 7 ; 44 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[3] ; R15 ; 7 ; 42 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[4] ; T15 ; 7 ; 39 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[5] ; U15 ; 7 ; 46 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[6] ; V15 ; 7 ; 46 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[7] ; W15 ; 7 ; 39 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[8] ; R14 ; 7 ; 42 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_ADDR[9] ; Y13 ; 7 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_CE_N ; M18 ; 6 ; 50 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; FL_OE_N ; AA15 ; 7 ; 35 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_RST_N ; W14 ; 7 ; 35 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_WE_N ; Y14 ; 7 ; 39 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX0[0] ; J2 ; 2 ; 0 ; 18 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX0[1] ; J1 ; 2 ; 0 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX0[2] ; H2 ; 2 ; 0 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX0[3] ; H1 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX0[4] ; F2 ; 2 ; 0 ; 20 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX0[5] ; F1 ; 2 ; 0 ; 20 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX0[6] ; E2 ; 2 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX1[0] ; E1 ; 2 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX1[1] ; H6 ; 2 ; 0 ; 21 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX1[2] ; H5 ; 2 ; 0 ; 21 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX1[3] ; H4 ; 2 ; 0 ; 21 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX1[4] ; G3 ; 2 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX1[5] ; D2 ; 2 ; 0 ; 22 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX1[6] ; D1 ; 2 ; 0 ; 22 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX2[0] ; G5 ; 2 ; 0 ; 22 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX2[1] ; G6 ; 2 ; 0 ; 23 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX2[2] ; C2 ; 2 ; 0 ; 23 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX2[3] ; C1 ; 2 ; 0 ; 23 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX2[4] ; E3 ; 2 ; 0 ; 24 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX2[5] ; E4 ; 2 ; 0 ; 24 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX2[6] ; D3 ; 2 ; 0 ; 25 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX3[0] ; F4 ; 2 ; 0 ; 23 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX3[1] ; D5 ; 2 ; 0 ; 24 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX3[2] ; D6 ; 2 ; 0 ; 24 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX3[3] ; J4 ; 2 ; 0 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX3[4] ; L8 ; 2 ; 0 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX3[5] ; F3 ; 2 ; 0 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; HEX3[6] ; D4 ; 2 ; 0 ; 25 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; I2C_SCLK ; A3 ; 3 ; 1 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDG[0] ; U22 ; 6 ; 50 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDG[1] ; U21 ; 6 ; 50 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDG[2] ; V22 ; 6 ; 50 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDG[3] ; V21 ; 6 ; 50 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDG[4] ; W22 ; 6 ; 50 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDG[5] ; W21 ; 6 ; 50 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDG[6] ; Y22 ; 6 ; 50 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDG[7] ; Y21 ; 6 ; 50 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDR[0] ; R20 ; 6 ; 50 ; 10 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDR[1] ; R19 ; 6 ; 50 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDR[2] ; U19 ; 6 ; 50 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDR[3] ; Y19 ; 6 ; 50 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDR[4] ; T18 ; 6 ; 50 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDR[5] ; V19 ; 6 ; 50 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDR[6] ; Y18 ; 6 ; 50 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDR[7] ; U18 ; 6 ; 50 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDR[8] ; R18 ; 6 ; 50 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; LEDR[9] ; R17 ; 6 ; 50 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SD_CLK ; F9 ; 3 ; 11 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; SRAM_ADDR[0] ; AA3 ; 8 ; 1 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[10] ; R11 ; 8 ; 20 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[11] ; T11 ; 8 ; 18 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[12] ; Y10 ; 8 ; 15 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[13] ; U10 ; 8 ; 13 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[14] ; R10 ; 8 ; 13 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[15] ; T7 ; 8 ; 5 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[16] ; Y6 ; 8 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[17] ; Y5 ; 8 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[1] ; AB3 ; 8 ; 1 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[2] ; AA4 ; 8 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[3] ; AB4 ; 8 ; 1 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[4] ; AA5 ; 8 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[5] ; AB10 ; 8 ; 22 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[6] ; AA11 ; 8 ; 24 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[7] ; AB11 ; 8 ; 24 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[8] ; V11 ; 8 ; 20 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_ADDR[9] ; W11 ; 8 ; 20 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_CE_N ; AB5 ; 8 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_LB_N ; Y7 ; 8 ; 5 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_OE_N ; T8 ; 8 ; 5 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_UB_N ; W7 ; 8 ; 9 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_WE_N ; AA10 ; 8 ; 22 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; TDO ; D7 ; 3 ; 9 ; 27 ; 2 ; yes ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; UART_TXD ; G12 ; 4 ; 31 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_B[0] ; A9 ; 3 ; 15 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_B[1] ; D11 ; 3 ; 22 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_B[2] ; A10 ; 3 ; 20 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_B[3] ; B10 ; 3 ; 20 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_G[0] ; B8 ; 3 ; 13 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_G[1] ; C10 ; 3 ; 18 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_G[2] ; B9 ; 3 ; 15 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_G[3] ; A8 ; 3 ; 13 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_HS ; A11 ; 3 ; 22 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_R[0] ; D9 ; 3 ; 13 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_R[1] ; C9 ; 3 ; 9 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_R[2] ; A7 ; 3 ; 11 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_R[3] ; B7 ; 3 ; 11 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; VGA_VS ; B11 ; 3 ; 22 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;+---------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Bidir Pins ;+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+; AUD_BCLK ; A4 ; 3 ; 1 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[0] ; U1 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[10] ; P1 ; 1 ; 0 ; 11 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[11] ; P2 ; 1 ; 0 ; 11 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[12] ; R1 ; 1 ; 0 ; 8 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[13] ; R2 ; 1 ; 0 ; 8 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[14] ; T1 ; 1 ; 0 ; 8 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[15] ; T2 ; 1 ; 0 ; 8 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[1] ; U2 ; 1 ; 0 ; 7 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[2] ; V1 ; 1 ; 0 ; 6 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[3] ; V2 ; 1 ; 0 ; 6 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[4] ; W1 ; 1 ; 0 ; 4 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[5] ; W2 ; 1 ; 0 ; 4 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[6] ; Y1 ; 1 ; 0 ; 4 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[7] ; Y2 ; 1 ; 0 ; 4 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[8] ; N1 ; 1 ; 0 ; 12 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; DRAM_DQ[9] ; N2 ; 1 ; 0 ; 12 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_DQ[0] ; AB16 ; 7 ; 35 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_DQ[1] ; AA16 ; 7 ; 35 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_DQ[2] ; AB17 ; 7 ; 37 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_DQ[3] ; AA17 ; 7 ; 37 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_DQ[4] ; AB18 ; 7 ; 42 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_DQ[5] ; AA18 ; 7 ; 44 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_DQ[6] ; AB19 ; 7 ; 48 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; FL_DQ[7] ; AA19 ; 7 ; 48 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[0] ; A13 ; 4 ; 26 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[10] ; A18 ; 4 ; 46 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[11] ; B18 ; 4 ; 46 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[12] ; A19 ; 4 ; 46 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[13] ; B19 ; 4 ; 46 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[14] ; A20 ; 4 ; 48 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[15] ; B20 ; 4 ; 48 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[16] ; C21 ; 5 ; 50 ; 24 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[17] ; C22 ; 5 ; 50 ; 24 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[18] ; D21 ; 5 ; 50 ; 21 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[19] ; D22 ; 5 ; 50 ; 22 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[1] ; B13 ; 4 ; 26 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[20] ; E21 ; 5 ; 50 ; 21 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[21] ; E22 ; 5 ; 50 ; 21 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[22] ; F21 ; 5 ; 50 ; 20 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[23] ; F22 ; 5 ; 50 ; 20 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[24] ; G21 ; 5 ; 50 ; 19 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[25] ; G22 ; 5 ; 50 ; 19 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[26] ; J21 ; 5 ; 50 ; 16 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[27] ; J22 ; 5 ; 50 ; 16 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[28] ; K21 ; 5 ; 50 ; 15 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[29] ; K22 ; 5 ; 50 ; 15 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[2] ; A14 ; 4 ; 29 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[30] ; J19 ; 5 ; 50 ; 17 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[31] ; J20 ; 5 ; 50 ; 16 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[32] ; J18 ; 5 ; 50 ; 17 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[33] ; K20 ; 5 ; 50 ; 17 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[34] ; L19 ; 5 ; 50 ; 15 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[35] ; L18 ; 5 ; 50 ; 15 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[3] ; B14 ; 4 ; 29 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[4] ; A15 ; 4 ; 33 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[5] ; B15 ; 4 ; 33 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[6] ; A16 ; 4 ; 33 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[7] ; B16 ; 4 ; 33 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[8] ; A17 ; 4 ; 37 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_0[9] ; B17 ; 4 ; 37 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[0] ; H12 ; 4 ; 31 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[10] ; C14 ; 4 ; 39 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[11] ; D14 ; 4 ; 35 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[12] ; D15 ; 4 ; 39 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[13] ; D16 ; 4 ; 42 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[14] ; C17 ; 4 ; 48 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[15] ; C18 ; 4 ; 48 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[16] ; C19 ; 5 ; 50 ; 24 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[17] ; C20 ; 5 ; 50 ; 25 ; 4 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[18] ; D19 ; 5 ; 50 ; 25 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[19] ; D20 ; 5 ; 50 ; 25 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[1] ; H13 ; 4 ; 37 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[20] ; E20 ; 5 ; 50 ; 23 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[21] ; F20 ; 5 ; 50 ; 23 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[22] ; E19 ; 5 ; 50 ; 25 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[23] ; E18 ; 5 ; 50 ; 25 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[24] ; G20 ; 5 ; 50 ; 23 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[25] ; G18 ; 5 ; 50 ; 22 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[26] ; G17 ; 5 ; 50 ; 22 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[27] ; H17 ; 5 ; 50 ; 20 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[28] ; J15 ; 5 ; 50 ; 18 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[29] ; H18 ; 5 ; 50 ; 20 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[2] ; H14 ; 4 ; 42 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[30] ; N22 ; 6 ; 50 ; 12 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[31] ; N21 ; 6 ; 50 ; 12 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[32] ; P15 ; 6 ; 50 ; 11 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[33] ; N15 ; 6 ; 50 ; 11 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[34] ; P17 ; 6 ; 50 ; 8 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[35] ; P18 ; 6 ; 50 ; 9 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[3] ; G15 ; 4 ; 39 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[4] ; E14 ; 4 ; 35 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[5] ; E15 ; 4 ; 42 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[6] ; F15 ; 4 ; 39 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[7] ; G16 ; 4 ; 44 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[8] ; F12 ; 4 ; 31 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; GPIO_1[9] ; F13 ; 4 ; 35 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; I2C_SDAT ; B3 ; 3 ; 1 ; 27 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SD_CMD ; C16 ; 4 ; 44 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; SD_DAT ; E7 ; 3 ; 5 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; SD_DAT3 ; G11 ; 3 ; 20 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; SRAM_DQ[0] ; AA6 ; 8 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[10] ; V9 ; 8 ; 9 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[11] ; U9 ; 8 ; 13 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[12] ; R9 ; 8 ; 13 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[13] ; W8 ; 8 ; 9 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[14] ; V8 ; 8 ; 9 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[15] ; U8 ; 8 ; 5 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[1] ; AB6 ; 8 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[2] ; AA7 ; 8 ; 11 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[3] ; AB7 ; 8 ; 11 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[4] ; AA8 ; 8 ; 15 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[5] ; AB8 ; 8 ; 15 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[6] ; AA9 ; 8 ; 18 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[7] ; AB9 ; 8 ; 18 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[8] ; Y9 ; 8 ; 11 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;; SRAM_DQ[9] ; W9 ; 8 ; 11 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------++------------------------------------------------------------+; I/O Bank Usage ;+----------+------------------+---------------+--------------+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;+----------+------------------+---------------+--------------+; 1 ; 40 / 41 ( 98 % ) ; 3.3V ; -- ;; 2 ; 32 / 33 ( 97 % ) ; 3.3V ; -- ;; 3 ; 31 / 43 ( 72 % ) ; 3.3V ; -- ;; 4 ; 39 / 40 ( 98 % ) ; 3.3V ; -- ;; 5 ; 36 / 39 ( 92 % ) ; 3.3V ; -- ;; 6 ; 32 / 36 ( 89 % ) ; 3.3V ; -- ;; 7 ; 35 / 40 ( 88 % ) ; 3.3V ; -- ;; 8 ; 41 / 43 ( 95 % ) ; 3.3V ; -- ;+----------+------------------+---------------+--------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; All Package Pins ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A3 ; 325 ; 3 ; I2C_SCLK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A4 ; 324 ; 3 ; AUD_BCLK ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A5 ; 322 ; 3 ; AUD_DACLRCK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A6 ; 320 ; 3 ; AUD_ADCLRCK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A7 ; 306 ; 3 ; VGA_R[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A8 ; 304 ; 3 ; VGA_G[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A9 ; 298 ; 3 ; VGA_B[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A10 ; 293 ; 3 ; VGA_B[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A11 ; 287 ; 3 ; VGA_HS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A12 ; 283 ; 4 ; CLOCK_24[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A13 ; 281 ; 4 ; GPIO_0[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A14 ; 279 ; 4 ; GPIO_0[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A15 ; 273 ; 4 ; GPIO_0[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A16 ; 271 ; 4 ; GPIO_0[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A17 ; 265 ; 4 ; GPIO_0[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A18 ; 251 ; 4 ; GPIO_0[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A19 ; 249 ; 4 ; GPIO_0[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A20 ; 247 ; 4 ; GPIO_0[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA3 ; 82 ; 8 ; SRAM_ADDR[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA4 ; 85 ; 8 ; SRAM_ADDR[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA5 ; 89 ; 8 ; SRAM_ADDR[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA6 ; 97 ; 8 ; SRAM_DQ[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA7 ; 103 ; 8 ; SRAM_DQ[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA8 ; 111 ; 8 ; SRAM_DQ[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA9 ; 114 ; 8 ; SRAM_DQ[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA10 ; 120 ; 8 ; SRAM_WE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA11 ; 122 ; 8 ; SRAM_ADDR[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA12 ; 128 ; 7 ; FL_ADDR[15] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA13 ; 130 ; 7 ; FL_ADDR[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA14 ; 136 ; 7 ; FL_ADDR[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA15 ; 138 ; 7 ; FL_OE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA16 ; 140 ; 7 ; FL_DQ[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA17 ; 144 ; 7 ; FL_DQ[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA18 ; 153 ; 7 ; FL_DQ[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA19 ; 162 ; 7 ; FL_DQ[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA20 ; 164 ; 7 ; FL_ADDR[17] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB3 ; 83 ; 8 ; SRAM_ADDR[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB4 ; 84 ; 8 ; SRAM_ADDR[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB5 ; 88 ; 8 ; SRAM_CE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB6 ; 96 ; 8 ; SRAM_DQ[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB7 ; 102 ; 8 ; SRAM_DQ[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB8 ; 110 ; 8 ; SRAM_DQ[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB9 ; 113 ; 8 ; SRAM_DQ[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB10 ; 119 ; 8 ; SRAM_ADDR[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB11 ; 121 ; 8 ; SRAM_ADDR[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB12 ; 127 ; 7 ; FL_ADDR[16] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB13 ; 129 ; 7 ; FL_ADDR[14] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB14 ; 135 ; 7 ; FL_ADDR[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB15 ; 137 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AB16 ; 139 ; 7 ; FL_DQ[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB17 ; 143 ; 7 ; FL_DQ[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB18 ; 152 ; 7 ; FL_DQ[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB19 ; 161 ; 7 ; FL_DQ[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB20 ; 163 ; 7 ; FL_ADDR[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B3 ; 326 ; 3 ; I2C_SDAT ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B4 ; 323 ; 3 ; AUD_XCK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B5 ; 321 ; 3 ; AUD_DACDAT ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B6 ; 319 ; 3 ; AUD_ADCDAT ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B7 ; 305 ; 3 ; VGA_R[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B8 ; 303 ; 3 ; VGA_G[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B9 ; 297 ; 3 ; VGA_G[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B10 ; 292 ; 3 ; VGA_B[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B11 ; 286 ; 3 ; VGA_VS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B12 ; 282 ; 4 ; CLOCK_24[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B13 ; 280 ; 4 ; GPIO_0[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B14 ; 278 ; 4 ; GPIO_0[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B15 ; 272 ; 4 ; GPIO_0[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B16 ; 270 ; 4 ; GPIO_0[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B17 ; 264 ; 4 ; GPIO_0[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B18 ; 250 ; 4 ; GPIO_0[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B19 ; 248 ; 4 ; GPIO_0[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B20 ; 246 ; 4 ; GPIO_0[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; C1 ; 8 ; 2 ; HEX2[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; C2 ; 9 ; 2 ; HEX2[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; C7 ; 315 ; 3 ; TCK ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; C9 ; 310 ; 3 ; VGA_R[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; C10 ; 296 ; 3 ; VGA_G[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; C13 ; 275 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C14 ; 260 ; 4 ; GPIO_1[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; C16 ; 254 ; 4 ; SD_CMD ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C17 ; 245 ; 4 ; GPIO_1[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; C18 ; 244 ; 4 ; GPIO_1[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; C19 ; 238 ; 5 ; GPIO_1[16] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; C20 ; 239 ; 5 ; GPIO_1[17] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; C21 ; 236 ; 5 ; GPIO_0[16] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; C22 ; 237 ; 5 ; GPIO_0[17] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; D1 ; 14 ; 2 ; HEX1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; D2 ; 15 ; 2 ; HEX1[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; D3 ; 2 ; 2 ; HEX2[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; D4 ; 3 ; 2 ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; D5 ; 4 ; 2 ; HEX3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; D6 ; 5 ; 2 ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; D7 ; 311 ; 3 ; TDO ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; D8 ; 309 ; 3 ; TCS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; D9 ; 302 ; 3 ; VGA_R[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; D11 ; 289 ; 3 ; VGA_B[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; D12 ; 284 ; 3 ; CLOCK_27[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; D14 ; 267 ; 4 ; GPIO_1[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; D15 ; 259 ; 4 ; GPIO_1[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; D16 ; 255 ; 4 ; GPIO_1[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; D19 ; 240 ; 5 ; GPIO_1[18] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; D20 ; 241 ; 5 ; GPIO_1[19] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; D21 ; 229 ; 5 ; GPIO_0[18] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; D22 ; 230 ; 5 ; GPIO_0[19] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; E1 ; 20 ; 2 ; HEX1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; E2 ; 21 ; 2 ; HEX0[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; E3 ; 6 ; 2 ; HEX2[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; E4 ; 7 ; 2 ; HEX2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; E7 ; 316 ; 3 ; SD_DAT ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; E8 ; 308 ; 3 ; TDI ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; E9 ; 301 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; E11 ; 288 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E12 ; 285 ; 3 ; CLOCK_27[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; E14 ; 266 ; 4 ; GPIO_1[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; E15 ; 256 ; 4 ; GPIO_1[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; E18 ; 243 ; 5 ; GPIO_1[23] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; E19 ; 242 ; 5 ; GPIO_1[22] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; E20 ; 234 ; 5 ; GPIO_1[20] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; E21 ; 227 ; 5 ; GPIO_0[20] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; E22 ; 228 ; 5 ; GPIO_0[21] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; F1 ; 22 ; 2 ; HEX0[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; F2 ; 23 ; 2 ; HEX0[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; F3 ; 13 ; 2 ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; F4 ; 10 ; 2 ; HEX3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;; F8 ; 312 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F9 ; 307 ; 3 ; SD_CLK ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; F10 ; 295 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F11 ; 294 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F12 ; 276 ; 4 ; GPIO_1[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; F13 ; 269 ; 4 ; GPIO_1[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; F14 ; 268 ; 4 ; UART_RXD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; F15 ; 262 ; 4 ; GPIO_1[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; F20 ; 235 ; 5 ; GPIO_1[21] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; F21 ; 223 ; 5 ; GPIO_0[22] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; F22 ; 224 ; 5 ; GPIO_0[23] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; G3 ; 16 ; 2 ; HEX1[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; G5 ; 12 ; 2 ; HEX2[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; G6 ; 11 ; 2 ; HEX2[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G8 ; 313 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; G11 ; 291 ; 3 ; SD_DAT3 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; G12 ; 277 ; 4 ; UART_TXD ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; G15 ; 261 ; 4 ; GPIO_1[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; G16 ; 252 ; 4 ; GPIO_1[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; G17 ; 231 ; 5 ; GPIO_1[26] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; G18 ; 232 ; 5 ; GPIO_1[25] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; G20 ; 233 ; 5 ; GPIO_1[24] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; G21 ; 221 ; 5 ; GPIO_0[24] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; G22 ; 222 ; 5 ; GPIO_0[25] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; H1 ; 24 ; 2 ; HEX0[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; H2 ; 25 ; 2 ; HEX0[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; H3 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H4 ; 17 ; 2 ; HEX1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; H5 ; 18 ; 2 ; HEX1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; H6 ; 19 ; 2 ; HEX1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H10 ; 299 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H11 ; 290 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H12 ; 274 ; 4 ; GPIO_1[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; H13 ; 263 ; 4 ; GPIO_1[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; H14 ; 257 ; 4 ; GPIO_1[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; H15 ; 253 ; 4 ; PS2_CLK ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; H16 ; 219 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H17 ; 226 ; 5 ; GPIO_1[27] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; H18 ; 225 ; 5 ; GPIO_1[29] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; H19 ; 214 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J1 ; 29 ; 2 ; HEX0[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; J2 ; 30 ; 2 ; HEX0[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J4 ; 28 ; 2 ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J14 ; 258 ; 4 ; PS2_DAT ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; J15 ; 220 ; 5 ; GPIO_1[28] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; J17 ; 218 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J18 ; 217 ; 5 ; GPIO_0[32] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; J19 ; 216 ; 5 ; GPIO_0[30] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; J20 ; 213 ; 5 ; GPIO_0[31] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; J21 ; 211 ; 5 ; GPIO_0[26] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; J22 ; 212 ; 5 ; GPIO_0[27] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K20 ; 215 ; 5 ; GPIO_0[33] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; K21 ; 209 ; 5 ; GPIO_0[28] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; K22 ; 210 ; 5 ; GPIO_0[29] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; L1 ; 38 ; 2 ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; L2 ; 39 ; 2 ; SW[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; L8 ; 26 ; 2 ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; L18 ; 208 ; 5 ; GPIO_0[35] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; L19 ; 207 ; 5 ; GPIO_0[34] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; L21 ; 205 ; 5 ; SW[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; L22 ; 206 ; 5 ; SW[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; M1 ; 41 ; 1 ; SW[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; M2 ; 42 ; 1 ; SW[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M5 ; 43 ; 1 ; DRAM_UDQM ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; M6 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;; M18 ; 202 ; 6 ; FL_CE_N ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; M19 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; M21 ; 203 ; 6 ; EXT_CLOCK ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; M22 ; 204 ; 6 ; SW[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; N1 ; 45 ; 1 ; DRAM_DQ[8] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; N2 ; 46 ; 1 ; DRAM_DQ[9] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; N3 ; 51 ; 1 ; DRAM_CKE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; N4 ; 52 ; 1 ; DRAM_ADDR[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; N6 ; 49 ; 1 ; DRAM_ADDR[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; N15 ; 194 ; 6 ; GPIO_1[33] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;; N21 ; 199 ; 6 ; GPIO_1[31] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; N22 ; 200 ; 6 ; GPIO_1[30] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; P1 ; 47 ; 1 ; DRAM_DQ[10] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; P2 ; 48 ; 1 ; DRAM_DQ[11] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; P3 ; 50 ; 1 ; DRAM_ADDR[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; P5 ; 55 ; 1 ; DRAM_ADDR[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; P6 ; 56 ; 1 ; DRAM_ADDR[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; P8 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; P9 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; P15 ; 193 ; 6 ; GPIO_1[32] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; P17 ; 186 ; 6 ; GPIO_1[34] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; P18 ; 187 ; 6 ; GPIO_1[35] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; R1 ; 57 ; 1 ; DRAM_DQ[12] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R2 ; 58 ; 1 ; DRAM_DQ[13] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; R5 ; 63 ; 1 ; DRAM_ADDR[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R6 ; 64 ; 1 ; DRAM_ADDR[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R7 ; 54 ; 1 ; DRAM_LDQM ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R8 ; 53 ; 1 ; DRAM_WE_N ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R9 ; 109 ; 8 ; SRAM_DQ[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; R10 ; 108 ; 8 ; SRAM_ADDR[14] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; R11 ; 116 ; 8 ; SRAM_ADDR[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; R12 ; 134 ; 7 ; FL_ADDR[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; R13 ; 145 ; 7 ; FL_ADDR[21] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; R14 ; 150 ; 7 ; FL_ADDR[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; R15 ; 151 ; 7 ; FL_ADDR[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; R16 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; R17 ; 177 ; 6 ; LEDR[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R18 ; 184 ; 6 ; LEDR[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R19 ; 185 ; 6 ; LEDR[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R20 ; 192 ; 6 ; LEDR[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R21 ; 190 ; 6 ; KEY[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; R22 ; 191 ; 6 ; KEY[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; T1 ; 59 ; 1 ; DRAM_DQ[14] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; T2 ; 60 ; 1 ; DRAM_DQ[15] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; T3 ; 69 ; 1 ; DRAM_CAS_N ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; T5 ; 67 ; 1 ; DRAM_RAS_N ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; T6 ; 68 ; 1 ; DRAM_CS_N ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; T7 ; 91 ; 8 ; SRAM_ADDR[15] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; T8 ; 90 ; 8 ; SRAM_OE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; T11 ; 115 ; 8 ; SRAM_ADDR[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; T12 ; 131 ; 7 ; FL_ADDR[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; T15 ; 147 ; 7 ; FL_ADDR[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; T16 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;; T18 ; 171 ; 6 ; LEDR[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; T21 ; 188 ; 6 ; KEY[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; T22 ; 189 ; 6 ; KEY[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; U1 ; 61 ; 1 ; DRAM_DQ[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; U2 ; 62 ; 1 ; DRAM_DQ[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; U3 ; 70 ; 1 ; DRAM_BA_0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; U4 ; 80 ; 1 ; DRAM_CLK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; U8 ; 92 ; 8 ; SRAM_DQ[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; U9 ; 106 ; 8 ; SRAM_DQ[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; U10 ; 107 ; 8 ; SRAM_ADDR[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; U11 ; 123 ; 8 ; SW[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; U12 ; 124 ; 8 ; SW[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; U13 ; 132 ; 7 ; FL_ADDR[20] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; U14 ; 146 ; 7 ; FL_ADDR[18] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; U15 ; 157 ; 7 ; FL_ADDR[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; U18 ; 170 ; 6 ; LEDR[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; U19 ; 172 ; 6 ; LEDR[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; U20 ; 176 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U21 ; 182 ; 6 ; LEDG[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; U22 ; 183 ; 6 ; LEDG[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; V1 ; 65 ; 1 ; DRAM_DQ[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; V2 ; 66 ; 1 ; DRAM_DQ[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V4 ; 81 ; 1 ; DRAM_BA_1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; V8 ; 98 ; 8 ; SRAM_DQ[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; V9 ; 101 ; 8 ; SRAM_DQ[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; V11 ; 118 ; 8 ; SRAM_ADDR[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; V12 ; 126 ; 7 ; SW[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; V14 ; 142 ; 7 ; FL_ADDR[19] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; V15 ; 158 ; 7 ; FL_ADDR[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;; V19 ; 166 ; 6 ; LEDR[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; V20 ; 173 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V21 ; 180 ; 6 ; LEDG[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; V22 ; 181 ; 6 ; LEDG[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; W1 ; 71 ; 1 ; DRAM_DQ[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; W2 ; 72 ; 1 ; DRAM_DQ[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; W3 ; 75 ; 1 ; DRAM_ADDR[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; W4 ; 76 ; 1 ; DRAM_ADDR[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; W5 ; 79 ; 1 ; DRAM_ADDR[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; W7 ; 99 ; 8 ; SRAM_UB_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; W8 ; 100 ; 8 ; SRAM_DQ[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; W9 ; 105 ; 8 ; SRAM_DQ[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W11 ; 117 ; 8 ; SRAM_ADDR[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; W12 ; 125 ; 7 ; SW[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W14 ; 141 ; 7 ; FL_RST_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; W15 ; 149 ; 7 ; FL_ADDR[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; W16 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; W21 ; 174 ; 6 ; LEDG[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; W22 ; 175 ; 6 ; LEDG[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; Y1 ; 73 ; 1 ; DRAM_DQ[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; Y2 ; 74 ; 1 ; DRAM_DQ[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; Y3 ; 77 ; 1 ; DRAM_ADDR[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; Y4 ; 78 ; 1 ; DRAM_ADDR[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; Y5 ; 86 ; 8 ; SRAM_ADDR[17] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; Y6 ; 87 ; 8 ; SRAM_ADDR[16] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; Y7 ; 93 ; 8 ; SRAM_LB_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; Y9 ; 104 ; 8 ; SRAM_DQ[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; Y10 ; 112 ; 8 ; SRAM_ADDR[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; Y13 ; 133 ; 7 ; FL_ADDR[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; Y14 ; 148 ; 7 ; FL_WE_N ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; Y16 ; 154 ; 7 ; FL_ADDR[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; Y17 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y18 ; 165 ; 6 ; LEDR[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; Y19 ; 168 ; 6 ; LEDR[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; Y20 ; 169 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; Y21 ; 178 ; 6 ; LEDG[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; Y22 ; 179 ; 6 ; LEDG[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+Note: Pin directions (input, output or bidir) are based on device operating in user mode.+------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PLL Summary ;+----------------------------------+--------------------------------------------------------------------------------+----------------------------------------------+; Name ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|pll ; VGA_Audio_PLL:p1|altpll:altpll_component|pll ;+----------------------------------+--------------------------------------------------------------------------------+----------------------------------------------+; SDC pin name ; u3|u1|sdram_pll1|altpll_component|pll ; p1|altpll_component|pll ;; PLL mode ; Normal ; Normal ;; Compensate clock ; clock0 ; clock0 ;; Compensated input/output pins ; -- ; -- ;; Self reset on gated loss of lock ; Off ; Off ;; Gate lock counter ; -- ; -- ;; Input frequency 0 ; 50.0 MHz ; 27.0 MHz ;; Input frequency 1 ; -- ; -- ;; Nominal PFD frequency ; 50.0 MHz ; 27.0 MHz ;; Nominal VCO frequency ; 800.0 MHz ; 377.9 MHz ;; VCO post scale ; -- ; 2 ;; VCO multiply ; -- ; -- ;; VCO divide ; -- ; -- ;; Freq min lock ; 31.25 MHz ; 21.43 MHz ;; Freq max lock ; 62.5 MHz ; 35.71 MHz ;; M VCO Tap ; 0 ; 0 ;; M Initial ; 1 ; 1 ;; M value ; 16 ; 14 ;; N value ; 1 ; 1 ;; Preserve PLL counter order ; Off ; Off ;; PLL location ; PLL_1 ; PLL_3 ;; Inclk0 signal ; CLOCK_50 ; CLOCK_27[0] ;; Inclk1 signal ; -- ; -- ;; Inclk0 signal type ; Dedicated Pin ; Dedicated Pin ;; Inclk1 signal type ; -- ; -- ;+----------------------------------+--------------------------------------------------------------------------------+----------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PLL Usage ;+----------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------+---------+---------------+------------+---------+---------+----------------------------------------------+; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Initial ; VCO Tap ; SDC Pin Name ;+----------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------+---------+---------------+------------+---------+---------+----------------------------------------------+; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; clock0 ; 1 ; 1 ; 50.0 MHz ; 0 (0 ps) ; 50/50 ; C0 ; 16 ; 8/8 Even ; 1 ; 0 ; u3|u1|sdram_pll1|altpll_component|pll|clk[0] ;; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk2 ; clock2 ; 1 ; 1 ; 50.0 MHz ; 0 (0 ps) ; 50/50 ; C2 ; 16 ; 8/8 Even ; 1 ; 0 ; u3|u1|sdram_pll1|altpll_component|pll|clk[2] ;; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; clock0 ; 14 ; 15 ; 25.2 MHz ; 0 (0 ps) ; 50/50 ; C0 ; 15 ; 8/7 Odd ; 1 ; 0 ; p1|altpll_component|pll|clk[0] ;; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; clock1 ; 2 ; 3 ; 18.0 MHz ; 0 (0 ps) ; 50/50 ; C1 ; 21 ; 11/10 Odd ; 1 ; 0 ; p1|altpll_component|pll|clk[1] ;+----------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------+---------+---------------+------------+---------+---------+----------------------------------------------++-------------------------------------------------------------------------------+; Output Pin Default Load For Reported TCO ;+----------------------------------+-------+------------------------------------+; I/O Standard ; Load ; Termination Resistance ;+----------------------------------+-------+------------------------------------+; 3.3-V LVTTL ; 0 pF ; Not Available ;; 3.3-V LVCMOS ; 0 pF ; Not Available ;; 2.5 V ; 0 pF ; Not Available ;; 1.8 V ; 0 pF ; Not Available ;; 1.5 V ; 0 pF ; Not Available ;; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;; LVDS ; 0 pF ; 100 Ohm (Differential) ;; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;; RSDS ; 0 pF ; 100 Ohm (Differential) ;; Simple RSDS ; 0 pF ; Not Available ;; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;+----------------------------------+-------+------------------------------------+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Resource Utilization by Entity ;+-------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;+-------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+; |CII_Starter_USB_API ; 2242 (2) ; 1092 (0) ; 1 (1) ; 208000 ; 51 ; 0 ; 0 ; 0 ; 283 ; 0 ; 1150 (2) ; 247 (0) ; 845 (1) ; |CII_Starter_USB_API ; work ;; |AUDIO_DAC:u11| ; 220 (220) ; 98 (98) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 122 (122) ; 24 (24) ; 74 (74) ; |CII_Starter_USB_API|AUDIO_DAC:u11 ; work ;; |CLK_LOCK:p0| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CII_Starter_USB_API|CLK_LOCK:p0 ; work ;; |CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CII_Starter_USB_API|CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component ; work ;; |CMD_Decode:u5| ; 381 (381) ; 299 (299) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 75 (75) ; 124 (124) ; 182 (182) ; |CII_Starter_USB_API|CMD_Decode:u5 ; work ;; |I2C_AV_Config:u10| ; 93 (45) ; 57 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 36 (10) ; 3 (0) ; 54 (35) ; |CII_Starter_USB_API|I2C_AV_Config:u10 ; work ;; |I2C_Controller:u0| ; 48 (48) ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 (26) ; 3 (3) ; 19 (19) ; |CII_Starter_USB_API|I2C_AV_Config:u10|I2C_Controller:u0 ; work ;; |Multi_Flash:u2| ; 186 (0) ; 120 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (0) ; 8 (0) ; 116 (0) ; |CII_Starter_USB_API|Multi_Flash:u2 ; work ;; |Flash_Controller:u1| ; 157 (157) ; 99 (99) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 58 (58) ; 8 (8) ; 91 (91) ; |CII_Starter_USB_API|Multi_Flash:u2|Flash_Controller:u1 ; work ;; |Flash_Multiplexer:u0| ; 66 (66) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 62 (62) ; |CII_Starter_USB_API|Multi_Flash:u2|Flash_Multiplexer:u0 ; work ;; |Multi_Sdram:u3| ; 295 (0) ; 220 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 73 (0) ; 50 (0) ; 172 (0) ; |CII_Starter_USB_API|Multi_Sdram:u3 ; work ;; |Sdram_Controller:u1| ; 286 (100) ; 215 (73) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 71 (27) ; 50 (29) ; 165 (44) ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1 ; work ;; |PLL1:sdram_pll1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1 ; work ;; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component ; work ;; |command:command1| ; 67 (67) ; 48 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 5 (5) ; 43 (43) ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|command:command1 ; work ;; |control_interface:control1| ; 87 (87) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 25 (25) ; 0 (0) ; 62 (62) ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1 ; work ;; |sdr_data_path:data_path1| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 16 (16) ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1 ; work ;; |Sdram_Multiplexer:u0| ; 49 (49) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 47 (47) ; |CII_Starter_USB_API|Multi_Sdram:u3|Sdram_Multiplexer:u0 ; work ;; |Multi_Sram:u6| ; 38 (38) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 35 (35) ; |CII_Starter_USB_API|Multi_Sram:u6 ; work ;; |Reset_Delay:d0| ; 33 (33) ; 26 (26) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 5 (5) ; 21 (21) ; |CII_Starter_USB_API|Reset_Delay:d0 ; work ;; |SEG7_LUT_4:u0| ; 28 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (0) ; 0 (0) ; 16 (0) ; |CII_Starter_USB_API|SEG7_LUT_4:u0 ; work ;; |SEG7_LUT:u0| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |CII_Starter_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u0 ; work ;; |SEG7_LUT:u1| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |CII_Starter_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u1 ; work ;; |SEG7_LUT:u2| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |CII_Starter_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u2 ; work ;; |SEG7_LUT:u3| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |CII_Starter_USB_API|SEG7_LUT_4:u0|SEG7_LUT:u3 ; work ;; |USB_JTAG:u1| ; 42 (13) ; 36 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 25 (10) ; 11 (3) ; |CII_Starter_USB_API|USB_JTAG:u1 ; work ;; |JTAG_REC:u0| ; 20 (20) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 15 (15) ; 4 (4) ; |CII_Starter_USB_API|USB_JTAG:u1|JTAG_REC:u0 ; work ;; |JTAG_TRANS:u1| ; 9 (9) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 4 (4) ; |CII_Starter_USB_API|USB_JTAG:u1|JTAG_TRANS:u1 ; work ;; |VGA_Audio_PLL:p1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CII_Starter_USB_API|VGA_Audio_PLL:p1 ; work ;; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CII_Starter_USB_API|VGA_Audio_PLL:p1|altpll:altpll_component ; work ;; |VGA_Controller:u8| ; 281 (281) ; 134 (134) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 131 (131) ; 7 (7) ; 143 (143) ; |CII_Starter_USB_API|VGA_Controller:u8 ; work ;; |VGA_OSD_RAM:u9| ; 460 (102) ; 43 (31) ; 0 (0) ; 208000 ; 51 ; 0 ; 0 ; 0 ; 0 ; 0 ; 416 (66) ; 1 (1) ; 43 (17) ; |CII_Starter_USB_API|VGA_OSD_RAM:u9 ; work ;; |Img_RAM:u0| ; 382 (0) ; 12 (0) ; 0 (0) ; 208000 ; 51 ; 0 ; 0 ; 0 ; 0 ; 0 ; 350 (0) ; 0 (0) ; 32 (0) ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0 ; work ;; |altsyncram:altsyncram_component| ; 382 (0) ; 12 (0) ; 0 (0) ; 208000 ; 51 ; 0 ; 0 ; 0 ; 0 ; 0 ; 350 (0) ; 0 (0) ; 32 (0) ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component ; work ;; |altsyncram_f7o1:auto_generated| ; 382 (0) ; 12 (0) ; 0 (0) ; 208000 ; 51 ; 0 ; 0 ; 0 ; 0 ; 0 ; 350 (0) ; 0 (0) ; 32 (0) ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated ; work ;; |altsyncram_e132:altsyncram1| ; 382 (12) ; 12 (12) ; 0 (0) ; 208000 ; 51 ; 0 ; 0 ; 0 ; 0 ; 0 ; 350 (0) ; 0 (0) ; 32 (6) ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1 ; work ;; |decode_qpa:decode_a| ; 65 (65) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 65 (65) ; 0 (0) ; 0 (0) ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a ; work ;; |mux_akb:mux5| ; 311 (311) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 285 (285) ; 0 (0) ; 26 (26) ; |CII_Starter_USB_API|VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|mux_akb:mux5 ; work ;; |ps2_keyboard:u4| ; 264 (264) ; 59 (59) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 205 (205) ; 0 (0) ; 59 (59) ; |CII_Starter_USB_API|ps2_keyboard:u4 ; work ;+-------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+----------------------------------------------------------------------------------------+; Delay Chain Summary ;+---------------+----------+---------------+---------------+-----------------------+-----+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;+---------------+----------+---------------+---------------+-----------------------+-----+; CLOCK_24[0] ; Input ; 0 ; 0 ; -- ; -- ;; CLOCK_24[1] ; Input ; 0 ; 0 ; -- ; -- ;; CLOCK_27[1] ; Input ; 0 ; 0 ; -- ; -- ;; EXT_CLOCK ; Input ; 0 ; 0 ; -- ; -- ;; KEY[1] ; Input ; 0 ; 0 ; -- ; -- ;; KEY[2] ; Input ; 0 ; 0 ; -- ; -- ;; KEY[3] ; Input ; 0 ; 0 ; -- ; -- ;; SW[2] ; Input ; 0 ; 0 ; -- ; -- ;; SW[3] ; Input ; 0 ; 0 ; -- ; -- ;; SW[4] ; Input ; 0 ; 0 ; -- ; -- ;; SW[5] ; Input ; 0 ; 0 ; -- ; -- ;; SW[6] ; Input ; 0 ; 0 ; -- ; -- ;; SW[7] ; Input ; 0 ; 0 ; -- ; -- ;; SW[8] ; Input ; 0 ; 0 ; -- ; -- ;; SW[9] ; Input ; 0 ; 0 ; -- ; -- ;; UART_RXD ; Input ; 0 ; 0 ; -- ; -- ;; AUD_ADCDAT ; Input ; 0 ; 0 ; -- ; -- ;; SW[1] ; Input ; 0 ; 0 ; -- ; -- ;; SW[0] ; Input ; 0 ; 0 ; -- ; -- ;; CLOCK_50 ; Input ; -- ; -- ; -- ; -- ;; KEY[0] ; Input ; 6 ; 6 ; -- ; -- ;; TCS ; Input ; 0 ; 0 ; -- ; -- ;; CLOCK_27[0] ; Input ; -- ; -- ; -- ; -- ;; TCK ; Input ; 0 ; 0 ; -- ; -- ;; TDI ; Input ; 0 ; 0 ; -- ; -- ;; PS2_CLK ; Input ; 6 ; 6 ; -- ; -- ;; PS2_DAT ; Input ; 6 ; 6 ; -- ; -- ;; HEX0[0] ; Output ; -- ; -- ; -- ; -- ;; HEX0[1] ; Output ; -- ; -- ; -- ; -- ;; HEX0[2] ; Output ; -- ; -- ; -- ; -- ;; HEX0[3] ; Output ; -- ; -- ; -- ; -- ;; HEX0[4] ; Output ; -- ; -- ; -- ; -- ;; HEX0[5] ; Output ; -- ; -- ; -- ; -- ;; HEX0[6] ; Output ; -- ; -- ; -- ; -- ;; HEX1[0] ; Output ; -- ; -- ; -- ; -- ;; HEX1[1] ; Output ; -- ; -- ; -- ; -- ;; HEX1[2] ; Output ; -- ; -- ; -- ; -- ;; HEX1[3] ; Output ; -- ; -- ; -- ; -- ;; HEX1[4] ; Output ; -- ; -- ; -- ; -- ;; HEX1[5] ; Output ; -- ; -- ; -- ; -- ;; HEX1[6] ; Output ; -- ; -- ; -- ; -- ;; HEX2[0] ; Output ; -- ; -- ; -- ; -- ;; HEX2[1] ; Output ; -- ; -- ; -- ; -- ;; HEX2[2] ; Output ; -- ; -- ; -- ; -- ;; HEX2[3] ; Output ; -- ; -- ; -- ; -- ;; HEX2[4] ; Output ; -- ; -- ; -- ; -- ;; HEX2[5] ; Output ; -- ; -- ; -- ; -- ;; HEX2[6] ; Output ; -- ; -- ; -- ; -- ;; HEX3[0] ; Output ; -- ; -- ; -- ; -- ;; HEX3[1] ; Output ; -- ; -- ; -- ; -- ;; HEX3[2] ; Output ; -- ; -- ; -- ; -- ;; HEX3[3] ; Output ; -- ; -- ; -- ; -- ;; HEX3[4] ; Output ; -- ; -- ; -- ; -- ;; HEX3[5] ; Output ; -- ; -- ; -- ; -- ;; HEX3[6] ; Output ; -- ; -- ; -- ; -- ;; LEDG[0] ; Output ; -- ; -- ; -- ; -- ;; LEDG[1] ; Output ; -- ; -- ; -- ; -- ;; LEDG[2] ; Output ; -- ; -- ; -- ; -- ;; LEDG[3] ; Output ; -- ; -- ; -- ; -- ;; LEDG[4] ; Output ; -- ; -- ; -- ; -- ;; LEDG[5] ; Output ; -- ; -- ; -- ; -- ;; LEDG[6] ; Output ; -- ; -- ; -- ; -- ;; LEDG[7] ; Output ; -- ; -- ; -- ; -- ;; LEDR[0] ; Output ; -- ; -- ; -- ; -- ;; LEDR[1] ; Output ; -- ; -- ; -- ; -- ;; LEDR[2] ; Output ; -- ; -- ; -- ; -- ;; LEDR[3] ; Output ; -- ; -- ; -- ; -- ;; LEDR[4] ; Output ; -- ; -- ; -- ; -- ;; LEDR[5] ; Output ; -- ; -- ; -- ; -- ;; LEDR[6] ; Output ; -- ; -- ; -- ; -- ;; LEDR[7] ; Output ; -- ; -- ; -- ; -- ;; LEDR[8] ; Output ; -- ; -- ; -- ; -- ;; LEDR[9] ; Output ; -- ; -- ; -- ; -- ;; UART_TXD ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[0] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[1] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[2] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[3] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[4] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[5] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[6] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[7] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[8] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[9] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[10] ; Output ; -- ; -- ; -- ; -- ;; DRAM_ADDR[11] ; Output ; -- ; -- ; -- ; -- ;; DRAM_LDQM ; Output ; -- ; -- ; -- ; -- ;; DRAM_UDQM ; Output ; -- ; -- ; -- ; -- ;; DRAM_WE_N ; Output ; -- ; -- ; -- ; -- ;; DRAM_CAS_N ; Output ; -- ; -- ; -- ; -- ;; DRAM_RAS_N ; Output ; -- ; -- ; -- ; -- ;; DRAM_CS_N ; Output ; -- ; -- ; -- ; -- ;; DRAM_BA_0 ; Output ; -- ; -- ; -- ; -- ;; DRAM_BA_1 ; Output ; -- ; -- ; -- ; -- ;; DRAM_CLK ; Output ; -- ; -- ; -- ; -- ;; DRAM_CKE ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[0] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[1] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[2] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[3] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[4] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[5] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[6] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[7] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[8] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[9] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[10] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[11] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[12] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[13] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[14] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[15] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[16] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[17] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[18] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[19] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[20] ; Output ; -- ; -- ; -- ; -- ;; FL_ADDR[21] ; Output ; -- ; -- ; -- ; -- ;; FL_WE_N ; Output ; -- ; -- ; -- ; -- ;; FL_RST_N ; Output ; -- ; -- ; -- ; -- ;; FL_OE_N ; Output ; -- ; -- ; -- ; -- ;; FL_CE_N ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[0] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[1] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[2] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[3] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[4] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[5] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[6] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[7] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[8] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[9] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[10] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[11] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[12] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[13] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[14] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[15] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[16] ; Output ; -- ; -- ; -- ; -- ;; SRAM_ADDR[17] ; Output ; -- ; -- ; -- ; -- ;; SRAM_UB_N ; Output ; -- ; -- ; -- ; -- ;; SRAM_LB_N ; Output ; -- ; -- ; -- ; -- ;; SRAM_WE_N ; Output ; -- ; -- ; -- ; -- ;; SRAM_CE_N ; Output ; -- ; -- ; -- ; -- ;; SRAM_OE_N ; Output ; -- ; -- ; -- ; -- ;; SD_CLK ; Output ; -- ; -- ; -- ; -- ;; TDO ; Output ; -- ; -- ; -- ; 0 ;; I2C_SCLK ; Output ; -- ; -- ; -- ; -- ;; VGA_HS ; Output ; -- ; -- ; -- ; -- ;; VGA_VS ; Output ; -- ; -- ; -- ; -- ;; VGA_R[0] ; Output ; -- ; -- ; -- ; -- ;; VGA_R[1] ; Output ; -- ; -- ; -- ; -- ;; VGA_R[2] ; Output ; -- ; -- ; -- ; -- ;; VGA_R[3] ; Output ; -- ; -- ; -- ; -- ;; VGA_G[0] ; Output ; -- ; -- ; -- ; -- ;; VGA_G[1] ; Output ; -- ; -- ; -- ; -- ;; VGA_G[2] ; Output ; -- ; -- ; -- ; -- ;; VGA_G[3] ; Output ; -- ; -- ; -- ; -- ;; VGA_B[0] ; Output ; -- ; -- ; -- ; -- ;; VGA_B[1] ; Output ; -- ; -- ; -- ; -- ;; VGA_B[2] ; Output ; -- ; -- ; -- ; -- ;; VGA_B[3] ; Output ; -- ; -- ; -- ; -- ;; AUD_ADCLRCK ; Output ; -- ; -- ; -- ; -- ;; AUD_DACLRCK ; Output ; -- ; -- ; -- ; -- ;; AUD_DACDAT ; Output ; -- ; -- ; -- ; -- ;; AUD_XCK ; Output ; -- ; -- ; -- ; -- ;; SD_DAT3 ; Bidir ; 0 ; 0 ; -- ; -- ;; SD_CMD ; Bidir ; 0 ; 0 ; -- ; -- ;; DRAM_DQ[0] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[1] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[2] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[3] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[4] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[5] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[6] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[7] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[8] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[9] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[10] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[11] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[12] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[13] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[14] ; Bidir ; 6 ; 6 ; -- ; -- ;; DRAM_DQ[15] ; Bidir ; 6 ; 6 ; -- ; -- ;; FL_DQ[0] ; Bidir ; 6 ; 6 ; -- ; -- ;; FL_DQ[1] ; Bidir ; 6 ; 6 ; -- ; -- ;; FL_DQ[2] ; Bidir ; 6 ; 6 ; -- ; -- ;; FL_DQ[3] ; Bidir ; 6 ; 6 ; -- ; -- ;; FL_DQ[4] ; Bidir ; 6 ; 6 ; -- ; -- ;; FL_DQ[5] ; Bidir ; 6 ; 6 ; -- ; -- ;; FL_DQ[6] ; Bidir ; 6 ; 6 ; -- ; -- ;; FL_DQ[7] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[0] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[1] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[2] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[3] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[4] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[5] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[6] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[7] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[8] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[9] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[10] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[11] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[12] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[13] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[14] ; Bidir ; 6 ; 6 ; -- ; -- ;; SRAM_DQ[15] ; Bidir ; 6 ; 6 ; -- ; -- ;; SD_DAT ; Bidir ; 0 ; 0 ; -- ; -- ;; I2C_SDAT ; Bidir ; 6 ; 6 ; -- ; -- ;; AUD_BCLK ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[0] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[1] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[2] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[3] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[4] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[5] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[6] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[7] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[8] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[9] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[10] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[11] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[12] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[13] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[14] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[15] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[16] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[17] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[18] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[19] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[20] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[21] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[22] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[23] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[24] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[25] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[26] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[27] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[28] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[29] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[30] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[31] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[32] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[33] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[34] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_0[35] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[0] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[1] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[2] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[3] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[4] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[5] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[6] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[7] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[8] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[9] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[10] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[11] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[12] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[13] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[14] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[15] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[16] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[17] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[18] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[19] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[20] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[21] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[22] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[23] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[24] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[25] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[26] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[27] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[28] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[29] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[30] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[31] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[32] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[33] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[34] ; Bidir ; 0 ; 0 ; -- ; -- ;; GPIO_1[35] ; Bidir ; 0 ; 0 ; -- ; -- ;+---------------+----------+---------------+---------------+-----------------------+-----++---------------------------------------------------------------------------------------------------------------------+; Pad To Core Delay Chain Fanout ;+---------------------------------------------------------------------------------------+-------------------+---------+; Source Pin / Fanout ; Pad To Core Index ; Setting ;+---------------------------------------------------------------------------------------+-------------------+---------+; CLOCK_24[0] ; ; ;; CLOCK_24[1] ; ; ;; CLOCK_27[1] ; ; ;; EXT_CLOCK ; ; ;; KEY[1] ; ; ;; KEY[2] ; ; ;; KEY[3] ; ; ;; SW[2] ; ; ;; SW[3] ; ; ;; SW[4] ; ; ;; SW[5] ; ; ;; SW[6] ; ; ;; SW[7] ; ; ;; SW[8] ; ; ;; SW[9] ; ; ;; UART_RXD ; ; ;; AUD_ADCDAT ; ; ;; SW[1] ; ; ;; SW[0] ; ; ;; CLOCK_50 ; ; ;; KEY[0] ; ; ;; - I2C_AV_Config:u10|mI2C_CTRL_CLK ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[8] ; 1 ; 6 ;; - CMD_Decode:u5|oSR_Select[0] ; 1 ; 6 ;; - CMD_Decode:u5|oSR_Select[1] ; 1 ; 6 ;; - CMD_Decode:u5|mSR_Start ; 1 ; 6 ;; - CMD_Decode:u5|mSDR_WRn ; 1 ; 6 ;; - CMD_Decode:u5|oLED_GREEN[0] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_GREEN[1] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_GREEN[2] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_GREEN[3] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_GREEN[4] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_GREEN[5] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_GREEN[6] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_GREEN[7] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_RED[0] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_RED[1] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_RED[2] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_RED[3] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_RED[4] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_RED[5] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_RED[6] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_RED[7] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_RED[8] ; 1 ; 6 ;; - CMD_Decode:u5|oLED_RED[9] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[15] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[14] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[13] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[12] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[11] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[10] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[9] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[8] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[7] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[6] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[5] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[4] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[3] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[2] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[1] ; 1 ; 6 ;; - CMD_Decode:u5|oSEG7_DIG[0] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[4] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.IDEL ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.P1 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.P2 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.P3 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.P4 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.P3_PRG ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.P3_DEV ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.P4_PRG ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.P6_CHP_ERA ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.READ ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|ST.P5 ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[5] ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[2] ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[3] ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[0] ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[1] ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|SD_COUNTER[4] ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|SCLK ; 1 ; 6 ;; - CMD_Decode:u5|f_SEG7 ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[63] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[62] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[61] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[59] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[56] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[57] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[60] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[58] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[7] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[3] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[4] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[0] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[6] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[2] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[5] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[1] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[9] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[10] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[11] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[12] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[13] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[14] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[15] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[16] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[17] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[18] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[19] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[20] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[21] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[22] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[23] ; 1 ; 6 ;; - CMD_Decode:u5|f_LED ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[24] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[25] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[26] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[27] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[28] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[29] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[30] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[31] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[32] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[33] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|ST[6] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|ST[8] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|ST[4] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|ST[5]~45 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|ST[2] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|ST[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|ST[3] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[2] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[4] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[5] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[8] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[9] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[10] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[11] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|Write ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|Read ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|WE_N ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CAS_N ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|RAS_N ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|BA[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|BA[1] ; 1 ; 6 ;; - CMD_Decode:u5|oFL_Select[0] ; 1 ; 6 ;; - CMD_Decode:u5|oFL_Select[1] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|mFL_Start ; 1 ; 6 ;; - CMD_Decode:u5|oFL_Start ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|preStart ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|r_ADDR[19]~22 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|mStart ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|mACT ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[3] ; 1 ; 6 ;; - CMD_Decode:u5|f_SRAM ; 1 ; 6 ;; - CMD_Decode:u5|oSR_ADDR[0]~56 ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[55] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[51] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[53] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[50] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[54] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[49] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[48] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[52] ; 1 ; 6 ;; - CMD_Decode:u5|mSR_ST.000 ; 1 ; 6 ;; - CMD_Decode:u5|f_SR_SEL ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[41] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[44] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[45] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[47] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[46] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[43] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[42] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[37] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[40] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[39] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[38] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[36] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[34] ; 1 ; 6 ;; - CMD_Decode:u5|CMD_Tmp[35] ; 1 ; 6 ;; - CMD_Decode:u5|mSR_ST.010 ; 1 ; 6 ;; - CMD_Decode:u5|mSR_ST.011 ; 1 ; 6 ;; - CMD_Decode:u5|mSR_ST.001 ; 1 ; 6 ;; - USB_JTAG:u1|oTxD_Done ; 1 ; 6 ;; - CMD_Decode:u5|mSR_ST.101 ; 1 ; 6 ;; - CMD_Decode:u5|mSR_ST.100 ; 1 ; 6 ;; - CMD_Decode:u5|oFL_TXD_Start ; 1 ; 6 ;; - CMD_Decode:u5|sel_SDR ; 1 ; 6 ;; - CMD_Decode:u5|oSDR_TXD_Start ; 1 ; 6 ;; - CMD_Decode:u5|oSR_TXD_Start ; 1 ; 6 ;; - CMD_Decode:u5|oPS2_TXD_Start ; 1 ; 6 ;; - CMD_Decode:u5|sel_SR ; 1 ; 6 ;; - CMD_Decode:u5|sel_FL ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_GO ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[11] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[2] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[3] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[4] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[5] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[6] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[7] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[8] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[9] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[10] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[12] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[13] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[14] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[15] ; 1 ; 6 ;; - VGA_OSD_RAM:u9|oBlue[9] ; 1 ; 6 ;; - VGA_OSD_RAM:u9|oRed[9]~34 ; 1 ; 6 ;; - VGA_OSD_RAM:u9|oRed[9]~23 ; 1 ; 6 ;; - CMD_Decode:u5|oOSD_CUR_EN[1] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_R[6] ; 1 ; 6 ;; - CMD_Decode:u5|oOSD_CUR_EN[0] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_X[0] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_X[1] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_Y[0] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_R[7] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_R[8] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_R[9] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_G[6] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_G[7] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_G[8] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_G[9] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_B[6] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_B[7] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_B[8] ; 1 ; 6 ;; - CMD_Decode:u5|oCursor_B[9] ; 1 ; 6 ;; - USB_JTAG:u1|oRxD_Ready ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[8] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_reada ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_writea ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_load_mode ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[1]~42 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|ST[5] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|ST[7] ; 1 ; 6 ;; - CMD_Decode:u5|mSDR_Start ; 1 ; 6 ;; - CMD_Decode:u5|oSDR_Select[1] ; 1 ; 6 ;; - CMD_Decode:u5|oSDR_Select[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|Pre_WR ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|Pre_RD ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|CMD_ACK ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[9] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[2] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[10] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[11] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[3] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[4] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[12] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[5] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[13] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[14] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[6] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[15] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[7] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[16] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[17] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_precharge ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[18] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_rw ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[19] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_refresh ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_flag ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|oe4 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[20] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|SADDR[21] ; 1 ; 6 ;; - CMD_Decode:u5|f_FLASH ; 1 ; 6 ;; - CMD_Decode:u5|oFL_TXD_DATA[7]~16 ; 1 ; 6 ;; - CMD_Decode:u5|mFL_ST.000 ; 1 ; 6 ;; - CMD_Decode:u5|f_FL_SEL ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|ST.10 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|ST.11 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|ST.01 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|mFinish ; 1 ; 6 ;; - CMD_Decode:u5|mFL_ST.101 ; 1 ; 6 ;; - CMD_Decode:u5|mFL_ST.011 ; 1 ; 6 ;; - CMD_Decode:u5|mFL_ST.001 ; 1 ; 6 ;; - CMD_Decode:u5|mFL_ST.110 ; 1 ; 6 ;; - CMD_Decode:u5|mFL_ST.111 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[3] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[4] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[5] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[6] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[7] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[8] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[9] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[10] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|mCLK ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[1] ; 1 ; 6 ;; - CMD_Decode:u5|oFL_CMD[0] ; 1 ; 6 ;; - CMD_Decode:u5|oFL_CMD[2] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|WE_CLK_Delay[2] ; 1 ; 6 ;; - USB_JTAG:u1|Pre_TxD_Done ; 1 ; 6 ;; - CMD_Decode:u5|f_SETUP ; 1 ; 6 ;; - CMD_Decode:u5|mSDR_ST.000 ; 1 ; 6 ;; - CMD_Decode:u5|mSDR_ST.001 ; 1 ; 6 ;; - CMD_Decode:u5|mSDR_ST.101 ; 1 ; 6 ;; - CMD_Decode:u5|mSDR_ST.011 ; 1 ; 6 ;; - CMD_Decode:u5|f_SDRAM ; 1 ; 6 ;; - CMD_Decode:u5|mPS2_ST.001 ; 1 ; 6 ;; - CMD_Decode:u5|f_PS2 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[5] ; 1 ; 6 ;; - CMD_Decode:u5|oFL_TXD_DATA[7]~17 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[13] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[5] ; 1 ; 6 ;; - CMD_Decode:u5|mSDR_ST.100 ; 1 ; 6 ;; - CMD_Decode:u5|mSDR_ST.010 ; 1 ; 6 ;; - CMD_Decode:u5|oSDR_TXD_DATA[7]~8 ; 1 ; 6 ;; - CMD_Decode:u5|oSR_TXD_DATA[7]~8 ; 1 ; 6 ;; - ps2_keyboard:u4|rx_ascii[5] ; 1 ; 6 ;; - ps2_keyboard:u4|m2_state ; 1 ; 6 ;; - ps2_keyboard:u4|rx_ascii[6] ; 1 ; 6 ;; - ps2_keyboard:u4|rx_ascii[0] ; 1 ; 6 ;; - ps2_keyboard:u4|rx_ascii[2] ; 1 ; 6 ;; - ps2_keyboard:u4|rx_ascii[4] ; 1 ; 6 ;; - ps2_keyboard:u4|rx_ascii[1] ; 1 ; 6 ;; - ps2_keyboard:u4|rx_ascii[3] ; 1 ; 6 ;; - CMD_Decode:u5|oPS2_TXD_DATA[6]~8 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[6] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[14] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[6] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[4] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[12] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[4] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[7] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[15] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[7] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[2] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[10] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[2] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[9] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[1] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[8] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[0] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[3] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[11] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DATAOUT[3] ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|END ; 1 ; 6 ;; - I2C_AV_Config:u10|mSetup_ST.10 ; 1 ; 6 ;; - I2C_AV_Config:u10|mSetup_ST.01 ; 1 ; 6 ;; - I2C_AV_Config:u10|LUT_INDEX[1] ; 1 ; 6 ;; - I2C_AV_Config:u10|LUT_INDEX[0] ; 1 ; 6 ;; - I2C_AV_Config:u10|LUT_INDEX[2] ; 1 ; 6 ;; - I2C_AV_Config:u10|LUT_INDEX[3] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[1] ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_CLK_DIV[0] ; 1 ; 6 ;; - VGA_OSD_RAM:u9|ADDR_dd[2] ; 1 ; 6 ;; - VGA_OSD_RAM:u9|ADDR_dd[0] ; 1 ; 6 ;; - VGA_OSD_RAM:u9|ADDR_dd[1] ; 1 ; 6 ;; - CMD_Decode:u5|f_VGA ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[1] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[5] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[2] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[6] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[3] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[7] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[4] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|mFL_DATA[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|OE ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[2] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[3] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[4] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[5] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[6] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[7] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[8] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[9] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[10] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[11] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[12] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[13] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[14] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN2[15] ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|SDO ; 1 ; 6 ;; - USB_JTAG:u1|Pre_RxD_Ready ; 1 ; 6 ;; - USB_JTAG:u1|oRxD_DATA[7]~8 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|READA ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_done ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_done ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|REF_REQ ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|INIT_REQ ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|WRITEA ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LOAD_MODE ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|DONE ; 1 ; 6 ;; - CMD_Decode:u5|f_SDR_SEL ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.10 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.11 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.01 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CM_ACK ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|PRECHARGE ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_shift[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|REFRESH ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|do_initial ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|ST.00 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[16] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[15] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[14] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[17] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[18] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[19] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[9] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[8] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[7] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[6] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[5] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[4] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[3] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[10] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[11] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[12] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[13] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[1] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[0] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[2] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[20] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_Finish[21] ; 1 ; 6 ;; - CMD_Decode:u5|mFL_ST.100 ; 1 ; 6 ;; - CMD_Decode:u5|mFL_ST.010 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[2] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[1] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Start_Delay[0] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[2] ; 1 ; 6 ;; - ps2_keyboard:u4|left_shift_key ; 1 ; 6 ;; - ps2_keyboard:u4|right_shift_key ; 1 ; 6 ;; - ps2_keyboard:u4|rx_ascii[0]~16 ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|ACK3 ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|ACK1 ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|ACK2 ; 1 ; 6 ;; - I2C_AV_Config:u10|mSetup_ST.00 ; 1 ; 6 ;; - VGA_OSD_RAM:u9|ADDR_d[2] ; 1 ; 6 ;; - VGA_OSD_RAM:u9|ADDR_d[0] ; 1 ; 6 ;; - VGA_OSD_RAM:u9|ADDR_d[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[2] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[3] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[4] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[5] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[6] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[7] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[8] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[9] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[10] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[11] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[12] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[13] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[14] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|sdr_data_path:data_path1|DIN1[15] ; 1 ; 6 ;; - CMD_Decode:u5|oSDR_ADDR[0]~66 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|CMD[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|CMD[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|ex_read ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|ex_write ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[2] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[3] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[4] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[5] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[6] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[7] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[8] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[9] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[10] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[11] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[12] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[13] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[14] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|timer[15] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|REF_ACK ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[6] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[7] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[8] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[9] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[10] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[11] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[12] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[13] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[14] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[15] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[0] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[4] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[5] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[2] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDONE ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|Pre_DONE ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Multiplexer:u0|ST.00 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_shift[1] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[0] ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Controller:u1|Cont_DIV[1] ; 1 ; 6 ;; - ps2_keyboard:u4|q~35 ; 1 ; 6 ;; - ps2_keyboard:u4|q[8]~36 ; 1 ; 6 ;; - ps2_keyboard:u4|q~37 ; 1 ; 6 ;; - ps2_keyboard:u4|q~38 ; 1 ; 6 ;; - ps2_keyboard:u4|q~39 ; 1 ; 6 ;; - ps2_keyboard:u4|always11~4 ; 1 ; 6 ;; - ps2_keyboard:u4|q~40 ; 1 ; 6 ;; - ps2_keyboard:u4|Equal70~99 ; 1 ; 6 ;; - ps2_keyboard:u4|q~41 ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state.m1_tx_wait_keyboard_ack ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[1] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift[1] ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state.m1_tx_wait_clk_h ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state~39 ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state~41 ; 1 ; 6 ;; - ps2_keyboard:u4|q~42 ; 1 ; 6 ;; - ps2_keyboard:u4|q~43 ; 1 ; 6 ;; - ps2_keyboard:u4|q~44 ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state.m1_tx_error_no_keyboard_ack ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state.m1_tx_done_recovery ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state~43 ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state.m1_rx_clk_l ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state.m1_tx_clk_h ; 1 ; 6 ;; - I2C_AV_Config:u10|mI2C_DATA[12]~96 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[2] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift[2] ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state.m1_tx_clk_l ; 1 ; 6 ;; - ps2_keyboard:u4|q~45 ; 1 ; 6 ;; - ps2_keyboard:u4|m1_state~45 ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[3] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_shift[3] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[4] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[5] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[6] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|command_delay[7] ; 1 ; 6 ;; - Multi_Sdram:u3|Sdram_Controller:u1|command:command1|CS_N[0]~4 ; 1 ; 6 ;; - VGA_Controller:u8|Add9~18_NEW_REG0 ; 1 ; 6 ;; - VGA_Controller:u8|Add9~16_NEW_REG2 ; 1 ; 6 ;; - VGA_Controller:u8|Add9~14_NEW_REG4 ; 1 ; 6 ;; - VGA_Controller:u8|Add9~12_NEW_REG6 ; 1 ; 6 ;; - VGA_Controller:u8|Add9~10_NEW_REG8 ; 1 ; 6 ;; - VGA_Controller:u8|Add9~8_NEW_REG10 ; 1 ; 6 ;; - VGA_Controller:u8|Add9~6_NEW_REG14 ; 1 ; 6 ;; - VGA_Controller:u8|Add9~4_NEW_REG16 ; 1 ; 6 ;; - VGA_Controller:u8|Add9~2_NEW_REG18 ; 1 ; 6 ;; - VGA_Controller:u8|Add9~0_NEW_REG20 ; 1 ; 6 ;; - VGA_Controller:u8|Add6~16_NEW_REG24 ; 1 ; 6 ;; - VGA_Controller:u8|Add6~14_NEW_REG26 ; 1 ; 6 ;; - VGA_Controller:u8|Add6~12_NEW_REG28 ; 1 ; 6 ;; - VGA_Controller:u8|Add6~10_NEW_REG30 ; 1 ; 6 ;; - VGA_Controller:u8|Add6~8_NEW_REG34 ; 1 ; 6 ;; - VGA_Controller:u8|Add6~6_NEW_REG36 ; 1 ; 6 ;; - VGA_Controller:u8|Add6~4_NEW_REG38 ; 1 ; 6 ;; - VGA_Controller:u8|Add6~2_NEW_REG42 ; 1 ; 6 ;; - VGA_Controller:u8|Add6~0_NEW_REG46 ; 1 ; 6 ;; - VGA_Controller:u8|Add8~18_NEW_REG122 ; 1 ; 6 ;; - VGA_Controller:u8|Add8~16_NEW_REG124 ; 1 ; 6 ;; - VGA_Controller:u8|Add8~14_NEW_REG126 ; 1 ; 6 ;; - VGA_Controller:u8|Add8~12_NEW_REG128 ; 1 ; 6 ;; - VGA_Controller:u8|Add8~10_NEW_REG130 ; 1 ; 6 ;; - VGA_Controller:u8|Add8~8_NEW_REG132 ; 1 ; 6 ;; - VGA_Controller:u8|Add8~6_NEW_REG136 ; 1 ; 6 ;; - VGA_Controller:u8|Add8~4_NEW_REG138 ; 1 ; 6 ;; - VGA_Controller:u8|Add8~2_NEW_REG140 ; 1 ; 6 ;; - VGA_Controller:u8|Add8~0_NEW_REG142 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~22_NEW_REG146 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~20_NEW_REG150 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~18_NEW_REG152 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~16_NEW_REG154 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~14_NEW_REG156 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~12_NEW_REG158 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~10_NEW_REG160 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~8_NEW_REG164 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~6_NEW_REG166 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~4_NEW_REG168 ; 1 ; 6 ;; - VGA_Controller:u8|Add10~2_NEW_REG170 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~22_NEW_REG172 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~20_NEW_REG176 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~18_NEW_REG178 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~16_NEW_REG180 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~14_NEW_REG182 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~12_NEW_REG186 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~10_NEW_REG188 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~8_NEW_REG190 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~6_NEW_REG194 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~4_NEW_REG198 ; 1 ; 6 ;; - VGA_Controller:u8|Add7~2_NEW_REG200 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[1]~8_NEW_REG204 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[5]~9_NEW_REG206 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[2]~10_NEW_REG208 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[6]~11_NEW_REG210 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[3]~12_NEW_REG212 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[7]~13_NEW_REG214 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[4]~14_NEW_REG216 ; 1 ; 6 ;; - Multi_Flash:u2|Flash_Multiplexer:u0|oAS1_DATA[0]~15_NEW_REG218 ; 1 ; 6 ;; - VGA_Controller:u8|Add5~18_NEW_REG220 ; 1 ; 6 ;; - VGA_Controller:u8|Add5~16_NEW_REG222 ; 1 ; 6 ;; - VGA_Controller:u8|Add5~14_NEW_REG224 ; 1 ; 6 ;; - VGA_Controller:u8|Add5~12_NEW_REG226 ; 1 ; 6 ;; - VGA_Controller:u8|Add5~10_NEW_REG230 ; 1 ; 6 ;; - VGA_Controller:u8|Add5~8_NEW_REG232 ; 1 ; 6 ;; - VGA_Controller:u8|Add5~6_NEW_REG234 ; 1 ; 6 ;; - VGA_Controller:u8|Add5~4_NEW_REG238 ; 1 ; 6 ;; - VGA_Controller:u8|Add5~2_NEW_REG242 ; 1 ; 6 ;; - VGA_Controller:u8|Add5~0_NEW_REG246 ; 1 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|SD[12]~25_RESYN336 ; 1 ; 6 ;; TCS ; ; ;; - TCS~clkctrl ; 0 ; 0 ;; CLOCK_27[0] ; ; ;; TCK ; ; ;; - CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component|clkctrl1 ; 0 ; 0 ;; TDI ; ; ;; - TDI~clkctrl ; 1 ; 0 ;; PS2_CLK ; ; ;; - ps2_keyboard:u4|ps2_clk_s ; 1 ; 6 ;; PS2_DAT ; ; ;; - ps2_keyboard:u4|ps2_data_s ; 0 ; 6 ;; SD_DAT3 ; ; ;; SD_CMD ; ; ;; DRAM_DQ[0] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[0] ; 0 ; 6 ;; DRAM_DQ[1] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[1] ; 1 ; 6 ;; DRAM_DQ[2] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[2] ; 1 ; 6 ;; DRAM_DQ[3] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[3]~feeder ; 0 ; 6 ;; DRAM_DQ[4] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[4] ; 1 ; 6 ;; DRAM_DQ[5] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[5] ; 1 ; 6 ;; DRAM_DQ[6] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[6]~feeder ; 1 ; 6 ;; DRAM_DQ[7] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[7]~feeder ; 1 ; 6 ;; DRAM_DQ[8] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[8]~feeder ; 0 ; 6 ;; DRAM_DQ[9] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[9] ; 1 ; 6 ;; DRAM_DQ[10] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[10] ; 1 ; 6 ;; DRAM_DQ[11] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[11]~feeder ; 1 ; 6 ;; DRAM_DQ[12] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[12] ; 1 ; 6 ;; DRAM_DQ[13] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[13]~feeder ; 1 ; 6 ;; DRAM_DQ[14] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[14] ; 1 ; 6 ;; DRAM_DQ[15] ; ; ;; - Multi_Sdram:u3|Sdram_Controller:u1|mDATAOUT[15]~feeder ; 1 ; 6 ;; FL_DQ[0] ; ; ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[0] ; 1 ; 6 ;; FL_DQ[1] ; ; ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[1] ; 1 ; 6 ;; FL_DQ[2] ; ; ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[2]~feeder ; 1 ; 6 ;; FL_DQ[3] ; ; ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[3] ; 1 ; 6 ;; FL_DQ[4] ; ; ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[4] ; 1 ; 6 ;; FL_DQ[5] ; ; ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[5]~feeder ; 0 ; 6 ;; FL_DQ[6] ; ; ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[6] ; 0 ; 6 ;; FL_DQ[7] ; ; ;; - Multi_Flash:u2|Flash_Controller:u1|oDATA[7]~feeder ; 0 ; 6 ;; SRAM_DQ[0] ; ; ;; - CMD_Decode:u5|Selector46~0 ; 0 ; 6 ;; SRAM_DQ[1] ; ; ;; - CMD_Decode:u5|Selector45~0 ; 1 ; 6 ;; SRAM_DQ[2] ; ; ;; - CMD_Decode:u5|Selector44~0 ; 1 ; 6 ;; SRAM_DQ[3] ; ; ;; - CMD_Decode:u5|Selector43~0 ; 0 ; 6 ;; SRAM_DQ[4] ; ; ;; - CMD_Decode:u5|Selector42~0 ; 0 ; 6 ;; - VGA_Controller:u8|Cur_Color_R[6]~20_RESYN250 ; 0 ; 6 ;; SRAM_DQ[5] ; ; ;; - CMD_Decode:u5|Selector41~0 ; 0 ; 6 ;; - VGA_Controller:u8|Cur_Color_R[7]~21_RESYN266 ; 0 ; 6 ;; SRAM_DQ[6] ; ; ;; - CMD_Decode:u5|Selector40~0 ; 0 ; 6 ;; - VGA_Controller:u8|Cur_Color_R[8]~22_RESYN268 ; 0 ; 6 ;; SRAM_DQ[7] ; ; ;; - CMD_Decode:u5|Selector39~0 ; 0 ; 6 ;; - mVIN_R[9]~0_RESYN312 ; 0 ; 6 ;; SRAM_DQ[8] ; ; ;; - CMD_Decode:u5|Selector46~0 ; 1 ; 6 ;; SRAM_DQ[9] ; ; ;; - CMD_Decode:u5|Selector45~0 ; 0 ; 6 ;; SRAM_DQ[10] ; ; ;; - CMD_Decode:u5|Selector44~0 ; 0 ; 6 ;; SRAM_DQ[11] ; ; ;; - CMD_Decode:u5|Selector43~0 ; 0 ; 6 ;; SRAM_DQ[12] ; ; ;; - CMD_Decode:u5|Selector42~0 ; 0 ; 6 ;; - VGA_Controller:u8|Cur_Color_R[6]~20_RESYN250 ; 0 ; 6 ;; SRAM_DQ[13] ; ; ;; - CMD_Decode:u5|Selector41~0 ; 0 ; 6 ;; - VGA_Controller:u8|Cur_Color_R[7]~21_RESYN266 ; 0 ; 6 ;; SRAM_DQ[14] ; ; ;; - CMD_Decode:u5|Selector40~0 ; 0 ; 6 ;; - VGA_Controller:u8|Cur_Color_R[8]~22_RESYN268 ; 0 ; 6 ;; SRAM_DQ[15] ; ; ;; - CMD_Decode:u5|Selector39~0 ; 1 ; 6 ;; - mVIN_R[9]~0_RESYN312 ; 1 ; 6 ;; SD_DAT ; ; ;; I2C_SDAT ; ; ;; - I2C_AV_Config:u10|I2C_Controller:u0|ACK3~1 ; 0 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|Selector4~0 ; 0 ; 6 ;; - I2C_AV_Config:u10|I2C_Controller:u0|ACK2~2 ; 0 ; 6 ;; AUD_BCLK ; ; ;; GPIO_0[0] ; ; ;; GPIO_0[1] ; ; ;; GPIO_0[2] ; ; ;; GPIO_0[3] ; ; ;; GPIO_0[4] ; ; ;; GPIO_0[5] ; ; ;; GPIO_0[6] ; ; ;; GPIO_0[7] ; ; ;; GPIO_0[8] ; ; ;; GPIO_0[9] ; ; ;; GPIO_0[10] ; ; ;; GPIO_0[11] ; ; ;; GPIO_0[12] ; ; ;; GPIO_0[13] ; ; ;; GPIO_0[14] ; ; ;; GPIO_0[15] ; ; ;; GPIO_0[16] ; ; ;; GPIO_0[17] ; ; ;; GPIO_0[18] ; ; ;; GPIO_0[19] ; ; ;; GPIO_0[20] ; ; ;; GPIO_0[21] ; ; ;; GPIO_0[22] ; ; ;; GPIO_0[23] ; ; ;; GPIO_0[24] ; ; ;; GPIO_0[25] ; ; ;; GPIO_0[26] ; ; ;; GPIO_0[27] ; ; ;; GPIO_0[28] ; ; ;; GPIO_0[29] ; ; ;; GPIO_0[30] ; ; ;; GPIO_0[31] ; ; ;; GPIO_0[32] ; ; ;; GPIO_0[33] ; ; ;; GPIO_0[34] ; ; ;; GPIO_0[35] ; ; ;; GPIO_1[0] ; ; ;; GPIO_1[1] ; ; ;; GPIO_1[2] ; ; ;; GPIO_1[3] ; ; ;; GPIO_1[4] ; ; ;; GPIO_1[5] ; ; ;; GPIO_1[6] ; ; ;; GPIO_1[7] ; ; ;; GPIO_1[8] ; ; ;; GPIO_1[9] ; ; ;; GPIO_1[10] ; ; ;; GPIO_1[11] ; ; ;; GPIO_1[12] ; ; ;; GPIO_1[13] ; ; ;; GPIO_1[14] ; ; ;; GPIO_1[15] ; ; ;; GPIO_1[16] ; ; ;; GPIO_1[17] ; ; ;; GPIO_1[18] ; ; ;; GPIO_1[19] ; ; ;; GPIO_1[20] ; ; ;; GPIO_1[21] ; ; ;; GPIO_1[22] ; ; ;; GPIO_1[23] ; ; ;; GPIO_1[24] ; ; ;; GPIO_1[25] ; ; ;; GPIO_1[26] ; ; ;; GPIO_1[27] ; ; ;; GPIO_1[28] ; ; ;; GPIO_1[29] ; ; ;; GPIO_1[30] ; ; ;; GPIO_1[31] ; ; ;; GPIO_1[32] ; ; ;; GPIO_1[33] ; ; ;; GPIO_1[34] ; ; ;; GPIO_1[35] ; ; ;+---------------------------------------------------------------------------------------+-------------------+---------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Control Signals ;+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+-----------------------------------------------------+--------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+-----------------------------------------------------+--------+----------------------+------------------+---------------------------+; AUDIO_DAC:u11|FLASH_Cont[0] ; LCFF_X39_Y14_N5 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; AUDIO_DAC:u11|LRCK_1X ; LCFF_X27_Y1_N13 ; 6 ; Clock ; yes ; Global Clock ; GCLK13 ; -- ;; AUDIO_DAC:u11|LRCK_2X ; LCFF_X49_Y14_N7 ; 16 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ;; AUDIO_DAC:u11|LRCK_4X ; LCFF_X26_Y1_N17 ; 38 ; Clock ; yes ; Global Clock ; GCLK14 ; -- ;; AUDIO_DAC:u11|LessThan1~2 ; LCCOMB_X27_Y1_N0 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ;; AUDIO_DAC:u11|LessThan2~2 ; LCCOMB_X49_Y14_N12 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ;; AUDIO_DAC:u11|LessThan3~1 ; LCCOMB_X26_Y1_N0 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ;; AUDIO_DAC:u11|oAUD_BCK ; LCFF_X27_Y2_N13 ; 7 ; Clock ; yes ; Global Clock ; GCLK12 ; -- ;; CLOCK_27[0] ; PIN_D12 ; 1 ; Clock ; no ; -- ; -- ; -- ;; CLOCK_50 ; PIN_L1 ; 2 ; Clock ; no ; -- ; -- ; -- ;; CLOCK_50 ; PIN_L1 ; 618 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;; CMD_Decode:u5|Decoder1~1 ; LCCOMB_X25_Y14_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|Decoder1~3 ; LCCOMB_X25_Y14_N16 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|Decoder1~4 ; LCCOMB_X25_Y14_N28 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|Decoder1~5 ; LCCOMB_X25_Y14_N20 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|Decoder1~6 ; LCCOMB_X26_Y14_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|Decoder1~7 ; LCCOMB_X25_Y14_N18 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|f_FLASH ; LCFF_X27_Y15_N19 ; 13 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|f_PS2 ; LCFF_X29_Y17_N31 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|f_SDRAM ; LCFF_X29_Y16_N31 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|f_SRAM ; LCFF_X26_Y16_N11 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oFL_ADDR[0]~66 ; LCCOMB_X26_Y15_N20 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oFL_TXD_DATA[7]~17 ; LCCOMB_X27_Y15_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oLED_GREEN[0]~9 ; LCCOMB_X25_Y14_N4 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oPS2_TXD_DATA[6]~8 ; LCCOMB_X32_Y15_N26 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oSDR_ADDR[0]~67 ; LCCOMB_X29_Y16_N20 ; 38 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oSDR_Select[1]~2 ; LCCOMB_X24_Y14_N8 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oSDR_TXD_DATA[7]~8 ; LCCOMB_X29_Y15_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oSEG7_DIG[0]~32 ; LCCOMB_X25_Y14_N24 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oSR_ADDR[0]~57 ; LCCOMB_X26_Y16_N0 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oSR_Select[1]~2 ; LCCOMB_X31_Y15_N8 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|oSR_TXD_DATA[7]~8 ; LCCOMB_X26_Y16_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; CMD_Decode:u5|sel_SDR~5 ; LCCOMB_X31_Y15_N12 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;; I2C_AV_Config:u10|I2C_Controller:u0|SD[12]~25 ; LCCOMB_X12_Y13_N4 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; I2C_AV_Config:u10|LessThan0~4 ; LCCOMB_X11_Y13_N8 ; 16 ; Sync. clear ; no ; -- ; -- ; -- ;; I2C_AV_Config:u10|LessThan1~0 ; LCCOMB_X10_Y13_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; LCFF_X11_Y13_N21 ; 40 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ;; I2C_AV_Config:u10|mI2C_DATA[12]~96 ; LCCOMB_X10_Y13_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; I2C_AV_Config:u10|mI2C_GO ; LCFF_X10_Y13_N9 ; 7 ; Sync. load ; no ; -- ; -- ; -- ;; KEY[0] ; PIN_R22 ; 588 ; Async. clear, Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ;; Multi_Flash:u2|Flash_Controller:u1|Equal1~0 ; LCCOMB_X27_Y15_N22 ; 11 ; Sync. clear ; no ; -- ; -- ; -- ;; Multi_Flash:u2|Flash_Controller:u1|ST.READ ; LCFF_X37_Y15_N23 ; 28 ; Output enable ; no ; -- ; -- ; -- ;; Multi_Flash:u2|Flash_Controller:u1|ST~90 ; LCCOMB_X37_Y15_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; Multi_Flash:u2|Flash_Controller:u1|always3~0 ; LCCOMB_X36_Y14_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; Multi_Flash:u2|Flash_Controller:u1|mACT ; LCFF_X37_Y16_N9 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;; Multi_Flash:u2|Flash_Controller:u1|mStart ; LCFF_X27_Y15_N15 ; 39 ; Sync. clear ; no ; -- ; -- ; -- ;; Multi_Flash:u2|Flash_Controller:u1|r_ADDR[19]~22 ; LCCOMB_X27_Y15_N20 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;; Multi_Sdram:u3|Sdram_Controller:u1|CMD[1]~9 ; LCCOMB_X30_Y18_N14 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; PLL_1 ; 197 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;; Multi_Sdram:u3|Sdram_Controller:u1|command:command1|OE ; LCFF_X16_Y11_N5 ; 16 ; Output enable ; no ; -- ; -- ; -- ;; Multi_Sdram:u3|Sdram_Controller:u1|command:command1|SA[1]~42 ; LCCOMB_X19_Y12_N28 ; 8 ; Sync. load ; no ; -- ; -- ; -- ;; Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rp_done~6 ; LCCOMB_X18_Y12_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|INIT_REQ ; LCFF_X13_Y12_N9 ; 26 ; Sync. clear ; no ; -- ; -- ; -- ;; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|LessThan0~3 ; LCCOMB_X12_Y12_N30 ; 15 ; Clock enable ; no ; -- ; -- ; -- ;; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|REF_REQ~5 ; LCCOMB_X20_Y10_N4 ; 16 ; Sync. load ; no ; -- ; -- ; -- ;; Multi_Sdram:u3|Sdram_Multiplexer:u0|oSDR_RD~2 ; LCCOMB_X29_Y18_N16 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;; Multi_Sram:u6|SRAM_WE_N~3 ; LCCOMB_X23_Y12_N28 ; 17 ; Output enable ; no ; -- ; -- ; -- ;; Reset_Delay:d0|Equal0~6 ; LCCOMB_X24_Y26_N4 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; Reset_Delay:d0|oRESET_OTERM371 ; LCFF_X25_Y26_N17 ; 84 ; Async. clear ; no ; -- ; -- ; -- ;; Reset_Delay:d0|oRESET_OTERM373 ; LCFF_X49_Y1_N1 ; 88 ; Async. clear ; no ; -- ; -- ; -- ;; TCK ; PIN_C7 ; 6 ; Clock ; yes ; Global Clock ; GCLK8 ; VCC ;; TCS ; PIN_D8 ; 17 ; Async. clear, Clock enable ; yes ; Global Clock ; GCLK7 ; -- ;; USB_JTAG:u1|JTAG_REC:u0|oRxD_DATA[7]~8 ; LCCOMB_X31_Y16_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; USB_JTAG:u1|mTCK ; LCFF_X1_Y13_N29 ; 19 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ;; USB_JTAG:u1|oRxD_DATA[7]~8 ; LCCOMB_X30_Y16_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; USB_JTAG:u1|oRxD_Ready ; LCFF_X30_Y16_N11 ; 68 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; PLL_3 ; 167 ; Clock ; yes ; Global Clock ; GCLK11 ; -- ;; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; PLL_3 ; 32 ; Clock ; yes ; Global Clock ; GCLK10 ; -- ;; VGA_Controller:u8|Cur_Color_B~21 ; LCCOMB_X30_Y12_N10 ; 4 ; Sync. load ; no ; -- ; -- ; -- ;; VGA_Controller:u8|Equal6~5 ; LCCOMB_X29_Y13_N14 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_Controller:u8|LessThan10~2 ; LCCOMB_X32_Y10_N30 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;; VGA_Controller:u8|LessThan8~5 ; LCCOMB_X29_Y11_N4 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;; VGA_Controller:u8|always0~5 ; LCCOMB_X29_Y12_N16 ; 39 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2842w[3] ; LCCOMB_X33_Y15_N4 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2859w[3] ; LCCOMB_X33_Y15_N2 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2869w[3]~2 ; LCCOMB_X32_Y14_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2879w[3] ; LCCOMB_X33_Y15_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2889w[3]~2 ; LCCOMB_X33_Y15_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2899w[3] ; LCCOMB_X33_Y15_N22 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2909w[3]~1 ; LCCOMB_X33_Y14_N16 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2919w[3] ; LCCOMB_X33_Y14_N2 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2942w[3] ; LCCOMB_X33_Y9_N8 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2953w[3] ; LCCOMB_X33_Y14_N28 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2963w[3] ; LCCOMB_X32_Y14_N18 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2973w[3] ; LCCOMB_X33_Y14_N8 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2983w[3] ; LCCOMB_X33_Y9_N14 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode2993w[3] ; LCCOMB_X32_Y14_N20 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3003w[3] ; LCCOMB_X33_Y9_N26 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3013w[3] ; LCCOMB_X33_Y14_N14 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3035w[3] ; LCCOMB_X33_Y9_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3046w[3] ; LCCOMB_X33_Y15_N20 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3056w[3] ; LCCOMB_X32_Y14_N22 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3066w[3] ; LCCOMB_X33_Y15_N14 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3076w[3] ; LCCOMB_X33_Y9_N22 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3086w[3] ; LCCOMB_X33_Y15_N16 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3096w[3] ; LCCOMB_X33_Y9_N20 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3106w[3] ; LCCOMB_X33_Y15_N26 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3128w[3] ; LCCOMB_X33_Y9_N10 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3139w[3] ; LCCOMB_X33_Y14_N20 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3149w[3] ; LCCOMB_X32_Y14_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3159w[3] ; LCCOMB_X33_Y14_N10 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3169w[3] ; LCCOMB_X33_Y9_N30 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3179w[3] ; LCCOMB_X32_Y14_N26 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3189w[3] ; LCCOMB_X33_Y9_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3199w[3] ; LCCOMB_X33_Y14_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3221w[3] ; LCCOMB_X33_Y9_N4 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3232w[3] ; LCCOMB_X33_Y15_N30 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3242w[3] ; LCCOMB_X32_Y14_N8 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3252w[3] ; LCCOMB_X33_Y15_N10 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3262w[3] ; LCCOMB_X33_Y9_N2 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3272w[3] ; LCCOMB_X33_Y15_N18 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3282w[3] ; LCCOMB_X33_Y9_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3292w[3] ; LCCOMB_X33_Y15_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3314w[3] ; LCCOMB_X33_Y9_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3325w[3] ; LCCOMB_X33_Y14_N4 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3335w[3] ; LCCOMB_X32_Y14_N10 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3345w[3] ; LCCOMB_X33_Y14_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3355w[3] ; LCCOMB_X33_Y9_N18 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3365w[3] ; LCCOMB_X32_Y14_N4 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3375w[3] ; LCCOMB_X33_Y9_N16 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3385w[3] ; LCCOMB_X33_Y14_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3407w[3]~3 ; LCCOMB_X33_Y9_N28 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3418w[3]~2 ; LCCOMB_X33_Y15_N28 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|decode_qpa:decode_a|w_anode3428w[3]~2 ; LCCOMB_X32_Y14_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ps2_keyboard:u4|WideOr0 ; LCCOMB_X38_Y8_N4 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ;; ps2_keyboard:u4|bit_count[0]~23 ; LCCOMB_X42_Y8_N8 ; 4 ; Sync. clear ; no ; -- ; -- ; -- ;; ps2_keyboard:u4|m1_state.m1_tx_wait_clk_h ; LCFF_X39_Y8_N19 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;; ps2_keyboard:u4|q[8]~36 ; LCCOMB_X45_Y7_N20 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;; ps2_keyboard:u4|rx_ascii[0]~16 ; LCCOMB_X42_Y8_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+-----------------------------------------------------+--------+----------------------+------------------+---------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Global & Other Fast Signals ;+----------------------------------------------------------------------------------+------------------+---------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+----------------------------------------------------------------------------------+------------------+---------+----------------------+------------------+---------------------------+; AUDIO_DAC:u11|LRCK_1X ; LCFF_X27_Y1_N13 ; 6 ; Global Clock ; GCLK13 ; -- ;; AUDIO_DAC:u11|LRCK_2X ; LCFF_X49_Y14_N7 ; 16 ; Global Clock ; GCLK6 ; -- ;; AUDIO_DAC:u11|LRCK_4X ; LCFF_X26_Y1_N17 ; 38 ; Global Clock ; GCLK14 ; -- ;; AUDIO_DAC:u11|oAUD_BCK ; LCFF_X27_Y2_N13 ; 7 ; Global Clock ; GCLK12 ; -- ;; CLOCK_50 ; PIN_L1 ; 618 ; Global Clock ; GCLK2 ; -- ;; I2C_AV_Config:u10|mI2C_CTRL_CLK ; LCFF_X11_Y13_N21 ; 40 ; Global Clock ; GCLK0 ; -- ;; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; PLL_1 ; 197 ; Global Clock ; GCLK3 ; -- ;; TCK ; PIN_C7 ; 6 ; Global Clock ; GCLK8 ; VCC ;; TCS ; PIN_D8 ; 17 ; Global Clock ; GCLK7 ; -- ;; TDI ; PIN_E8 ; 2 ; Global Clock ; GCLK15 ; -- ;; USB_JTAG:u1|mTCK ; LCFF_X1_Y13_N29 ; 19 ; Global Clock ; GCLK1 ; -- ;; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 ; PLL_3 ; 167 ; Global Clock ; GCLK11 ; -- ;; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; PLL_3 ; 32 ; Global Clock ; GCLK10 ; -- ;+----------------------------------------------------------------------------------+------------------+---------+----------------------+------------------+---------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------+; Non-Global High Fan-Out Signals ;+-------------------------------------------------------------------------------------------------------------------------------------------+---------+; Name ; Fan-Out ;+-------------------------------------------------------------------------------------------------------------------------------------------+---------+; KEY[0] ; 588 ;; ~GND ; 522 ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|out_address_reg_a[0] ; 169 ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|out_address_reg_a[1] ; 147 ;; Reset_Delay:d0|oRESET_OTERM373 ; 88 ;; Reset_Delay:d0|oRESET_OTERM371 ; 84 ;; USB_JTAG:u1|oRxD_Ready ; 68 ;; ps2_keyboard:u4|q[5] ; 65 ;; ps2_keyboard:u4|q[4] ; 60 ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|out_address_reg_a[2] ; 58 ;; VGA_OSD_RAM:u9|Add3~32 ; 52 ;; VGA_OSD_RAM:u9|Add3~20 ; 51 ;; VGA_OSD_RAM:u9|Add3~18 ; 51 ;; VGA_OSD_RAM:u9|Add3~16 ; 51 ;; VGA_OSD_RAM:u9|Add3~14 ; 51 ;; VGA_OSD_RAM:u9|Add3~12 ; 51 ;; VGA_OSD_RAM:u9|Add3~10 ; 51 ;; VGA_OSD_RAM:u9|Add3~8 ; 51 ;; VGA_OSD_RAM:u9|Add3~6 ; 51 ;; VGA_OSD_RAM:u9|Add3~4 ; 51 ;; CMD_Decode:u5|oSDR_Select[0] ; 48 ;; CMD_Decode:u5|oSDR_Select[1] ; 48 ;; AUDIO_DAC:u11|SEL_Cont[0] ; 48 ;; CMD_Decode:u5|oFL_Select[1] ; 47 ;; CMD_Decode:u5|oFL_Select[0] ; 47 ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|out_address_reg_a[3] ; 46 ;; VGA_Controller:u8|always0~5 ; 39 ;; Multi_Flash:u2|Flash_Controller:u1|mStart ; 39 ;; AUDIO_DAC:u11|SEL_Cont[1] ; 39 ;; CMD_Decode:u5|oSR_Select[1] ; 39 ;; CMD_Decode:u5|oSR_Select[0] ; 39 ;; CMD_Decode:u5|oSDR_ADDR[0]~67 ; 38 ;; VGA_OSD_RAM:u9|Add3~30 ; 38 ;; VGA_OSD_RAM:u9|Add3~28 ; 38 ;; AUDIO_DAC:u11|SEL_Cont[3] ; 36 ;; CMD_Decode:u5|oSR_ADDR[0]~57 ; 34 ;; Multi_Flash:u2|Flash_Controller:u1|mACT ; 34 ;; AUDIO_DAC:u11|SEL_Cont[2] ; 34 ;; CMD_Decode:u5|Decoder1~5 ; 32 ;; CMD_Decode:u5|Decoder1~4 ; 32 ;; Multi_Flash:u2|Flash_Controller:u1|r_ADDR[19]~22 ; 32 ;; CMD_Decode:u5|oFL_ADDR[0]~66 ; 30 ;; Multi_Flash:u2|Flash_Controller:u1|ST.READ ; 28 ;; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|INIT_REQ ; 26 ;; VGA_OSD_RAM:u9|Add3~22 ; 25 ;; ps2_keyboard:u4|q[1] ; 25 ;; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|out_address_reg_a[4] ; 25 ;; AUDIO_DAC:u11|SIN_Cont[1] ; 25 ;; Multi_Flash:u2|Flash_Controller:u1|ST.P4_PRG ; 25 ;; ps2_keyboard:u4|Equal70~43 ; 24 ;+-------------------------------------------------------------------------------------------------------------------------------------------+---------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter RAM Summary;+---------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location;+---------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ALTSYNCRAM ; M4K ; True Dual Port ; Single Clock ; 26000 ; 8 ; 208000 ; 1 ; yes ; yes ; yes ; no ; 208000 ; 26000 ; 8 ; 208000 ; 1 ; 208000 ; 51 ; Img_DATA.hex ; M4K_X41_Y12, M4K_X17_Y18, M4K_X41_Y26, M4K_X41_Y8, M4K_X41_Y15, M4K_X41_Y22, M4K_X41_Y18, M4K_X41_Y13, M4K_X41_Y23, M4K_X41_Y20, M4K_X41_Y19, M4K_X41_Y16, M4K_X41_Y21, M4K_X41_Y24, M4K_X41_Y7, M4K_X41_Y1, M4K_X17_Y11, M4K_X17_Y7, M4K_X17_Y9, M4K_X17_Y25, M4K_X17_Y22, M4K_X17_Y23, M4K_X17_Y21, M4K_X17_Y19, M4K_X17_Y24, M4K_X17_Y20, M4K_X17_Y13, M4K_X17_Y3, M4K_X17_Y2, M4K_X17_Y8, M4K_X17_Y1, M4K_X17_Y12, M4K_X17_Y10, M4K_X17_Y6, M4K_X17_Y4, M4K_X17_Y15, M4K_X17_Y16, M4K_X17_Y14, M4K_X17_Y17, M4K_X41_Y3, M4K_X41_Y14, M4K_X41_Y10, M4K_X41_Y11, M4K_X41_Y17, M4K_X41_Y2, M4K_X41_Y25, M4K_X41_Y9, M4K_X41_Y6, M4K_X41_Y4, M4K_X41_Y5, M4K_X17_Y5 ;+---------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.+-----------------------------------------------------+; Interconnect Usage Summary ;+----------------------------+------------------------+; Interconnect Resource Type ; Usage ;+----------------------------+------------------------+; Block interconnects ; 3,811 / 54,004 ( 7 % ) ;; C16 interconnects ; 96 / 2,100 ( 5 % ) ;; C4 interconnects ; 2,528 / 36,000 ( 7 % ) ;; Direct links ; 450 / 54,004 ( < 1 % ) ;; Global clocks ; 13 / 16 ( 81 % ) ;; Local interconnects ; 1,029 / 18,752 ( 5 % ) ;; R24 interconnects ; 150 / 1,900 ( 8 % ) ;; R4 interconnects ; 3,190 / 46,920 ( 7 % ) ;+----------------------------+------------------------++-----------------------------------------------------------------------------+; LAB Logic Elements ;+---------------------------------------------+-------------------------------+; Number of Logic Elements (Average = 11.81) ; Number of LABs (Total = 190) ;+---------------------------------------------+-------------------------------+; 1 ; 30 ;; 2 ; 4 ;; 3 ; 1 ;; 4 ; 6 ;; 5 ; 3 ;; 6 ; 0 ;; 7 ; 2 ;; 8 ; 1 ;; 9 ; 2 ;; 10 ; 6 ;; 11 ; 8 ;; 12 ; 5 ;; 13 ; 6 ;; 14 ; 8 ;; 15 ; 3 ;; 16 ; 105 ;+---------------------------------------------+-------------------------------++--------------------------------------------------------------------+; LAB-wide Signals ;+------------------------------------+-------------------------------+; LAB-wide Signals (Average = 1.67) ; Number of LABs (Total = 190) ;+------------------------------------+-------------------------------+; 1 Async. clear ; 84 ;; 1 Clock ; 110 ;; 1 Clock enable ; 51 ;; 1 Sync. clear ; 14 ;; 1 Sync. load ; 3 ;; 2 Async. clears ; 8 ;; 2 Clock enables ; 15 ;; 2 Clocks ; 32 ;+------------------------------------+-------------------------------++------------------------------------------------------------------------------+; LAB Signals Sourced ;+----------------------------------------------+-------------------------------+; Number of Signals Sourced (Average = 17.08) ; Number of LABs (Total = 190) ;+----------------------------------------------+-------------------------------+; 0 ; 0 ;; 1 ; 17 ;; 2 ; 15 ;; 3 ; 0 ;; 4 ; 4 ;; 5 ; 2 ;; 6 ; 1 ;; 7 ; 0 ;; 8 ; 4 ;; 9 ; 0 ;; 10 ; 4 ;; 11 ; 4 ;; 12 ; 6 ;; 13 ; 2 ;; 14 ; 7 ;; 15 ; 1 ;; 16 ; 18 ;; 17 ; 4 ;; 18 ; 8 ;; 19 ; 4 ;; 20 ; 5 ;; 21 ; 9 ;; 22 ; 7 ;; 23 ; 10 ;; 24 ; 8 ;; 25 ; 11 ;; 26 ; 3 ;; 27 ; 4 ;; 28 ; 14 ;; 29 ; 6 ;; 30 ; 4 ;; 31 ; 4 ;; 32 ; 4 ;+----------------------------------------------+-------------------------------++---------------------------------------------------------------------------------+; LAB Signals Sourced Out ;+-------------------------------------------------+-------------------------------+; Number of Signals Sourced Out (Average = 8.31) ; Number of LABs (Total = 190) ;+-------------------------------------------------+-------------------------------+; 0 ; 0 ;; 1 ; 40 ;; 2 ; 7 ;; 3 ; 5 ;; 4 ; 10 ;; 5 ; 4 ;; 6 ; 9 ;; 7 ; 7 ;; 8 ; 8 ;; 9 ; 12 ;; 10 ; 16 ;; 11 ; 12 ;; 12 ; 12 ;; 13 ; 10 ;; 14 ; 11 ;; 15 ; 5 ;; 16 ; 12 ;; 17 ; 3 ;; 18 ; 1 ;; 19 ; 3 ;; 20 ; 2 ;; 21 ; 0 ;; 22 ; 1 ;+-------------------------------------------------+-------------------------------++------------------------------------------------------------------------------+; LAB Distinct Inputs ;+----------------------------------------------+-------------------------------+; Number of Distinct Inputs (Average = 15.16) ; Number of LABs (Total = 190) ;+----------------------------------------------+-------------------------------+; 0 ; 0 ;; 1 ; 0 ;; 2 ; 26 ;; 3 ; 7 ;; 4 ; 7 ;; 5 ; 8 ;; 6 ; 6 ;; 7 ; 4 ;; 8 ; 5 ;; 9 ; 5 ;; 10 ; 6 ;; 11 ; 4 ;; 12 ; 5 ;; 13 ; 5 ;; 14 ; 3 ;; 15 ; 2 ;; 16 ; 7 ;; 17 ; 3 ;; 18 ; 10 ;; 19 ; 5 ;; 20 ; 11 ;; 21 ; 6 ;; 22 ; 1 ;; 23 ; 5 ;; 24 ; 6 ;; 25 ; 6 ;; 26 ; 1 ;; 27 ; 1 ;; 28 ; 2 ;; 29 ; 5 ;; 30 ; 20 ;; 31 ; 5 ;; 32 ; 1 ;; 33 ; 1 ;+----------------------------------------------+-------------------------------++-------------------------------------------------------------------------+; Fitter Device Options ;+----------------------------------------------+--------------------------+; Option ; Setting ;+----------------------------------------------+--------------------------+; Enable user-supplied start-up clock (CLKUSR) ; Off ;; Enable device-wide reset (DEV_CLRn) ; Off ;; Enable device-wide output enable (DEV_OE) ; Off ;; Enable INIT_DONE output ; Off ;; Configuration scheme ; Active Serial ;; Error detection CRC ; Off ;; nCEO ; As output driving ground ;; ASDO,nCSO ; As input tri-stated ;; Reserve all unused pins ; As output driving ground ;; Base pin-out file on sameframe device ; Off ;+----------------------------------------------+--------------------------++------------------------------------+; Operating Settings and Conditions ;+---------------------------+--------+; Setting ; Value ;+---------------------------+--------+; Nominal Core Voltage ; 1.20 V ;+---------------------------+--------++------------------------------------------------------------+; Estimated Delay Added for Hold Timing ;+-----------------+----------------------+-------------------+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;+-----------------+----------------------+-------------------++----------------------------+; Advanced Data - General ;+--------------------+-------+; Name ; Value ;+--------------------+-------+; Status Code ; 0 ;; Desired User Slack ; 0 ;; Fit Attempts ; 1 ;+--------------------+-------++------------------------------------------------------------------------------------------------+; Advanced Data - Placement Preparation ;+------------------------------------------------------------------+-----------------------------+; Name ; Value ;+------------------------------------------------------------------+-----------------------------+; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3076 ;; LE/ALM Count - Fit Attempt 1 ; 2234 ;; LAB Count - Fit Attempt 1 ; 182 ;; Outputs per Lab - Fit Attempt 1 ; 8.659 ;; Inputs per LAB - Fit Attempt 1 ; 14.736 ;; Global Inputs per LAB - Fit Attempt 1 ; 1.082 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:177;1:5 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:76;1:39;2:45;3:21;4:1 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:72;1:24;2:57;3:26;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:179;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:48;1:87;2:27;3:19;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:87;1:40;2:55 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:84;1:86;2:12 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:48;1:65;2:69 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:48;1:95;2:39 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:115;1:67 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:160;1:22 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:172;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:126;2:30;3:21;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Time in tsm_tan.dll - Fit Attempt 1 ; 0.156 ;+------------------------------------------------------------------+-----------------------------++------------------------------------------------------------------------------------------------+; Advanced Data - Placement ;+------------------------------------------------------------------+-----------------------------+; Name ; Value ;+------------------------------------------------------------------+-----------------------------+; Auto Fit Point 2 - Fit Attempt 1 ; ff ;; Early Wire Use - Fit Attempt 1 ; 4 ;; Early Slack - Fit Attempt 1 ; -10588 ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -8675 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -8675 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Late Wire Use - Fit Attempt 1 ; 8 ;; Late Slack - Fit Attempt 1 ; -8675 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3076 ;; LE/ALM Count - Fit Attempt 1 ; 2234 ;; LAB Count - Fit Attempt 1 ; 182 ;; Outputs per Lab - Fit Attempt 1 ; 8.659 ;; Inputs per LAB - Fit Attempt 1 ; 14.742 ;; Global Inputs per LAB - Fit Attempt 1 ; 1.082 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:177;1:5 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:76;1:39;2:45;3:21;4:1 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:72;1:24;2:57;3:26;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:179;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:48;1:87;2:27;3:19;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:87;1:40;2:55 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:84;1:86;2:12 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:48;1:65;2:69 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:48;1:95;2:39 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:113;1:69 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:160;1:22 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:172;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:126;2:30;3:21;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3081 ;; LE/ALM Count - Fit Attempt 1 ; 2239 ;; LAB Count - Fit Attempt 1 ; 186 ;; Outputs per Lab - Fit Attempt 1 ; 8.500 ;; Inputs per LAB - Fit Attempt 1 ; 14.613 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.919 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:181;1:5 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:76;1:26;2:55;3:26;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:76;1:24;2:57;3:26;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:183;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:48;1:104;2:31;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:83;1:33;2:63;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:88;1:86;2:12 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:48;1:69;2:69 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:48;1:99;2:39 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:117;1:69 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:164;1:22 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:176;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:130;2:30;3:21;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3088 ;; LE/ALM Count - Fit Attempt 1 ; 2243 ;; LAB Count - Fit Attempt 1 ; 190 ;; Outputs per Lab - Fit Attempt 1 ; 8.337 ;; Inputs per LAB - Fit Attempt 1 ; 14.405 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.926 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:185;1:5 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:76;1:28;2:59;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:76;1:26;2:61;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:187;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:48;1:107;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:83;1:35;2:65;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:90;1:89;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:48;1:72;2:70 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:48;1:102;2:40 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:121;1:69 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:169;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:180;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:133;2:30;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -4656 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -8675 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 8 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3088 ;; LE/ALM Count - Fit Attempt 1 ; 2244 ;; LAB Count - Fit Attempt 1 ; 192 ;; Outputs per Lab - Fit Attempt 1 ; 8.271 ;; Inputs per LAB - Fit Attempt 1 ; 14.307 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.922 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:187;1:5 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:77;1:29;2:59;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:77;1:27;2:61;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:189;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:49;1:108;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:84;1:36;2:65;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:92;1:89;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:49;1:73;2:70 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:49;1:103;2:40 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:123;1:69 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:171;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:182;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:135;2:30;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -8717 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -8717 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 8 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3096 ;; LE/ALM Count - Fit Attempt 1 ; 2252 ;; LAB Count - Fit Attempt 1 ; 197 ;; Outputs per Lab - Fit Attempt 1 ; 8.086 ;; Inputs per LAB - Fit Attempt 1 ; 14.102 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.909 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:192;1:5 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:80;1:31;2:59;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:80;1:29;2:61;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:194;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:52;1:110;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:87;1:38;2:65;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:96;1:90;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:52;1:75;2:70 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:52;1:105;2:40 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:128;1:69 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:176;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:187;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:139;2:31;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -5226 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -8717 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 8 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3096 ;; LE/ALM Count - Fit Attempt 1 ; 2252 ;; LAB Count - Fit Attempt 1 ; 197 ;; Outputs per Lab - Fit Attempt 1 ; 8.081 ;; Inputs per LAB - Fit Attempt 1 ; 14.096 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.909 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:192;1:5 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:80;1:31;2:59;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:80;1:29;2:61;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:194;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:52;1:110;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:87;1:38;2:65;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:96;1:90;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:52;1:75;2:70 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:52;1:105;2:40 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:128;1:69 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:176;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:187;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:139;2:31;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -5177 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -8717 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3088 ;; LE/ALM Count - Fit Attempt 1 ; 2243 ;; LAB Count - Fit Attempt 1 ; 190 ;; Outputs per Lab - Fit Attempt 1 ; 8.337 ;; Inputs per LAB - Fit Attempt 1 ; 14.405 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.926 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:185;1:5 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:76;1:28;2:59;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:76;1:26;2:61;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:187;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:48;1:107;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:83;1:35;2:65;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:90;1:89;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:48;1:72;2:70 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:48;1:102;2:40 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:121;1:69 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:169;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:180;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:133;2:30;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 8 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3115 ;; LE/ALM Count - Fit Attempt 1 ; 2271 ;; LAB Count - Fit Attempt 1 ; 204 ;; Outputs per Lab - Fit Attempt 1 ; 7.922 ;; Inputs per LAB - Fit Attempt 1 ; 13.740 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.912 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:198;1:6 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:80;1:35;2:62;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:80;1:33;2:64;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:201;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:52;1:117;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:87;1:43;2:67;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:99;1:94;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:52;1:82;2:70 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:52;1:112;2:40 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:133;1:71 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:183;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:194;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:145;2:32;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -8835 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -8786 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 8 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3120 ;; LE/ALM Count - Fit Attempt 1 ; 2276 ;; LAB Count - Fit Attempt 1 ; 205 ;; Outputs per Lab - Fit Attempt 1 ; 7.893 ;; Inputs per LAB - Fit Attempt 1 ; 13.785 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.917 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:199;1:6 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:79;1:36;2:63;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:79;1:34;2:65;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:202;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:51;1:119;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:86;1:43;2:69;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:98;1:96;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:51;1:84;2:70 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:51;1:113;2:41 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:134;1:71 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:184;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:195;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:143;2:35;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -9152 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -9152 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 8 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3120 ;; LE/ALM Count - Fit Attempt 1 ; 2275 ;; LAB Count - Fit Attempt 1 ; 206 ;; Outputs per Lab - Fit Attempt 1 ; 7.850 ;; Inputs per LAB - Fit Attempt 1 ; 13.718 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.917 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:200;1:6 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:79;1:38;2:62;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:79;1:36;2:64;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:203;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:51;1:120;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:86;1:45;2:68;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:99;1:96;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:51;1:86;2:69 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:51;1:115;2:40 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:135;1:71 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:185;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:196;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:144;2:35;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -9152 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -9152 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 8 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3120 ;; LE/ALM Count - Fit Attempt 1 ; 2275 ;; LAB Count - Fit Attempt 1 ; 205 ;; Outputs per Lab - Fit Attempt 1 ; 7.888 ;; Inputs per LAB - Fit Attempt 1 ; 13.785 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.917 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:199;1:6 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:79;1:36;2:63;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:79;1:34;2:65;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:202;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:51;1:119;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:86;1:43;2:69;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:98;1:96;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:51;1:84;2:70 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:51;1:113;2:41 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:134;1:71 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:184;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:195;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:143;2:35;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -9152 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -9152 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3088 ;; LE/ALM Count - Fit Attempt 1 ; 2243 ;; LAB Count - Fit Attempt 1 ; 190 ;; Outputs per Lab - Fit Attempt 1 ; 8.337 ;; Inputs per LAB - Fit Attempt 1 ; 14.405 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.926 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:185;1:5 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:76;1:28;2:59;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:76;1:26;2:61;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:187;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:48;1:107;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:83;1:35;2:65;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:90;1:89;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:48;1:72;2:70 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:48;1:102;2:40 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:121;1:69 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:169;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:180;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:133;2:30;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 7 ;; Mid Slack - Fit Attempt 1 ; -12152 ;; Internal Atom Count - Fit Attempt 1 ; 3088 ;; LE/ALM Count - Fit Attempt 1 ; 2243 ;; LAB Count - Fit Attempt 1 ; 190 ;; Outputs per Lab - Fit Attempt 1 ; 8.337 ;; Inputs per LAB - Fit Attempt 1 ; 14.405 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.926 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:185;1:5 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:76;1:28;2:59;3:24;4:3 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:76;1:26;2:61;3:24;4:3 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:187;1:1;2:2 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:48;1:107;2:32;3:2;4:1 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:83;1:35;2:65;3:7 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:90;1:89;2:11 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:48;1:72;2:70 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:48;1:102;2:40 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:121;1:69 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:169;1:21 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:180;1:10 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:133;2:30;3:22;4:3;5:1 ;; LEs in Chains - Fit Attempt 1 ; 387 ;; LEs in Long Chains - Fit Attempt 1 ; 98 ;; LABs with Chains - Fit Attempt 1 ; 39 ;; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;; Time - Fit Attempt 1 ; 1 ;; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;; Auto Fit Point 7 - Fit Attempt 1 ; ff ;; Time - Fit Attempt 1 ; 58 ;; Time in fit_fsyn.dll - Fit Attempt 1 ; 42.875 ;; Time in tsm_tan.dll - Fit Attempt 1 ; 9.313 ;+------------------------------------------------------------------+-----------------------------++---------------------------------------------------+; Advanced Data - Routing ;+-------------------------------------+-------------+; Name ; Value ;+-------------------------------------+-------------+; Early Slack - Fit Attempt 1 ; -7923 ;; Early Wire Use - Fit Attempt 1 ; 8 ;; Peak Regional Wire - Fit Attempt 1 ; 12 ;; Mid Slack - Fit Attempt 1 ; -8565 ;; Late Slack - Fit Attempt 1 ; -2147483648 ;; Late Wire Use - Fit Attempt 1 ; 7 ;; Time - Fit Attempt 1 ; 6 ;; Time in tsm_tan.dll - Fit Attempt 1 ; 3.078 ;+-------------------------------------+-------------++-----------------+; Fitter Messages ;+-----------------+Info: *******************************************************************Info: Running Quartus II FitterInfo: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web EditionInfo: Processing started: Sun Oct 11 12:23:22 2009Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off CII_Starter_USB_API -c CII_Starter_USB_APIInfo: Selected device EP2C20F484C7 for design "CII_Starter_USB_API"Info: Implemented PLL "Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|pll" as Cyclone II PLL typeInfo: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 portInfo: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk2 portInfo: Implemented PLL "VGA_Audio_PLL:p1|altpll:altpll_component|pll" as Cyclone II PLL typeInfo: Implementing clock multiplication of 14, clock division of 15, and phase shift of 0 degrees (0 ps) for VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 portInfo: Implementing clock multiplication of 2, clock division of 3, and phase shift of 0 degrees (0 ps) for VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 portInfo: Found following RAM instances in design that are actually implemented ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a37" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a38" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a36" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a39" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a33" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a34" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a32" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a35" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a41" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a40" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a43" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a42" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a47" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a45" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a46" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a44" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a50" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a48" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a49" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a5" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a6" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a4" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a7" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a1" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a2" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a0" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a3" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a12" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a8" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a14" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a10" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a13" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a9" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a15" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a11" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a21" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a22" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a20" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a23" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a17" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a18" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a16" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a19" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a27" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a25" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a26" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a24" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a31" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a29" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a30" is instantiated as RAM, but it actually implements ROM function because the write is always disabledInfo: Atom "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a28" is instantiated as RAM, but it actually implements ROM function because the write is always disabledWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a37" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a38" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a36" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a39" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a33" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a34" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a32" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a35" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a41" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a40" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a43" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a42" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a47" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a45" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a46" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a44" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a50" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a48" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a49" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a5" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a6" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a4" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a7" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a1" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a2" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a0" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a3" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a12" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a8" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a14" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a10" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a13" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a9" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a15" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a11" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a21" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a22" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a20" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a23" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a17" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a18" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a16" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a19" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a27" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a25" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a26" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a24" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a31" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a29" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a30" has a port clk1 that is stuck at GNDWarning (15400): WYSIWYG primitive "VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_f7o1:auto_generated|altsyncram_e132:altsyncram1|ram_block2a28" has a port clk1 that is stuck at GNDInfo: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation timeWarning: Feature LogicLock is not available with your current licenseInfo: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devicesInfo: Device EP2C15AF484C7 is compatibleInfo: Device EP2C35F484C7 is compatibleInfo: Device EP2C50F484C7 is compatibleInfo: Fitter converted 3 user pins into dedicated programming pinsInfo: Pin ~ASDO~ is reserved at location C4Info: Pin ~nCSO~ is reserved at location C3Info: Pin ~LVDS91p/nCEO~ is reserved at location W20Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.Info: Clock Control Block CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component|wire_clkctrl1_outclk has its enable register mode parameter set to NONE, but its inclk[0] port is driven by block TCK. De-asserting the ena signal on the Clock Control during a high-pulse of the specified clock input signal can cause a glitch on the clock output.Warning: No exact pin location assignment(s) for 5 pins of 283 total pinsInfo: Pin FL_CE_N not assigned to an exact location on the deviceInfo: Pin SD_CLK not assigned to an exact location on the deviceInfo: Pin SD_DAT3 not assigned to an exact location on the deviceInfo: Pin SD_CMD not assigned to an exact location on the deviceInfo: Pin SD_DAT not assigned to an exact location on the deviceInfo: Fitter is using the TimeQuest Timing AnalyzerCritical Warning: Synopsys Design Constraints File file not found: 'CII_Starter_USB_API.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.Info: No user constrained generated clocks found in the design.Info: No user constrained base clocks found in the design.Info: Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.Info: Automatically promoted node CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input))Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2Info: Automatically promoted node Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 (placed in counter C0 of PLL_1)Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3Info: Automatically promoted node Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk2 (placed in counter C2 of PLL_1)Info: Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_X0_Y1_N1Info: Promoted node TCKInfo: Automatically promoted CLK_LOCK:p0|CLK_LOCK_altclkctrl_tb8:CLK_LOCK_altclkctrl_tb8_component|clkctrl1 to use location or clock signal Global ClockInfo: Pin TCK drives global or regional clock Global Clock, but is not placed in a dedicated clock pin positionInfo: Promoted node TCSInfo: Promoted destinations to use location or clock signal Global ClockInfo: Pin TCS drives global or regional clock Global Clock, but is not placed in a dedicated clock pin positionInfo: Promoted node TDIInfo: Promoted destinations to use location or clock signal Global ClockInfo: Pin TDI drives global or regional clock Global Clock, but is not placed in a dedicated clock pin positionInfo: Automatically promoted node VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 (placed in counter C0 of PLL_3)Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11Info: Automatically promoted node VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 (placed in counter C1 of PLL_3)Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G10Info: Automatically promoted node I2C_AV_Config:u10|mI2C_CTRL_CLKInfo: Automatically promoted destinations to use location or clock signal Global ClockInfo: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node I2C_AV_Config:u10|I2C_Controller:u0|I2C_SCLK~2Info: Destination node I2C_AV_Config:u10|mI2C_CTRL_CLK~2Info: Automatically promoted node AUDIO_DAC:u11|LRCK_4XInfo: Automatically promoted destinations to use location or clock signal Global ClockInfo: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node AUDIO_DAC:u11|LRCK_4X~0Info: Automatically promoted node USB_JTAG:u1|mTCKInfo: Automatically promoted destinations to use location or clock signal Global ClockInfo: Automatically promoted node AUDIO_DAC:u11|LRCK_2XInfo: Automatically promoted destinations to use location or clock signal Global ClockInfo: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node AUDIO_DAC:u11|LRCK_2X~0Info: Automatically promoted node AUDIO_DAC:u11|LRCK_1XInfo: Automatically promoted destinations to use location or clock signal Global ClockInfo: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node AUD_DACLRCKInfo: Destination node AUD_ADCLRCKInfo: Destination node AUDIO_DAC:u11|LRCK_1X~0Info: Automatically promoted node AUDIO_DAC:u11|oAUD_BCKInfo: Automatically promoted destinations to use location or clock signal Global ClockInfo: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node AUD_BCLKInfo: Destination node AUDIO_DAC:u11|oAUD_BCK~0Info: Automatically promoted node Reset_Delay:d0|oRESETInfo: Automatically promoted destinations to use location or clock signal Global ClockInfo: Starting register packingExtra Info: Performing register packing on registers with non-logic cell location assignmentsExtra Info: Completed register packing on registers with non-logic cell location assignmentsExtra Info: Started Fast Input/Output/OE register processingInfo: Ignoring invalid fast I/O register assignmentsExtra Info: Finished Fast Input/Output/OE register processingExtra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and densityExtra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocksInfo: Finished register packingExtra Info: Packed 1 registers into blocks of type I/OInfo: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placementInfo: Number of I/O pins in group: 5 (unused VREF, 3.3V VCCIO, 0 input, 2 output, 3 bidirectional)Info: I/O standards used: 3.3-V LVTTL.Info: I/O bank details before I/O pin placementInfo: Statistics of I/O banksInfo: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 40 total pin(s) used -- 1 pins availableInfo: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 32 total pin(s) used -- 1 pins availableInfo: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used -- 15 pins availableInfo: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 2 pins availableInfo: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used -- 3 pins availableInfo: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 31 total pin(s) used -- 5 pins availableInfo: I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 35 total pin(s) used -- 5 pins availableInfo: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 2 pins availableWarning: PLL "VGA_Audio_PLL:p1|altpll:altpll_component|pll" output port clk[1] feeds output pin "AUD_XCK" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performanceInfo: Starting physical synthesis optimizations for speedInfo: Starting physical synthesis algorithm automatic asynchronous signal pipeliningInfo: Automatic asynchronous signal pipelining - Evaluation PhaseInfo: Asynchronous signal |CII_Starter_USB_API|KEY[0]Info: Signal not critical. No action is requiredInfo: Asynchronous signal |CII_Starter_USB_API|Reset_Delay:d0|oRESET~clkctrlInfo: Signal is criticalInfo: The signal will be pipelined in the Execution PhaseInfo: Asynchronous signal |CII_Starter_USB_API|TCS~clkctrlInfo: Signal not critical. No action is requiredInfo: Found 3 asynchronous signals of which 1 will be pipelinedInfo: Physical synthesis algorithm automatic asynchronous signal pipelining completeInfo: Starting physical synthesis algorithm register retimingInfo: Physical synthesis algorithm register retiming complete: estimated slack improvement of 2999 psInfo: Starting physical synthesis algorithm combinational resynthesis using boolean divisionInfo: Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 410 psInfo: Starting physical synthesis algorithm register retimingInfo: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 psInfo: Physical synthesis optimizations for speed complete: elapsed cpu time is 00:00:18Info: Fitter preparation operations ending: elapsed time is 00:00:24Info: Fitter placement preparation operations beginningInfo: Fitter placement preparation operations ending: elapsed time is 00:00:01Info: Fitter placement operations beginningInfo: Fitter placement was successfulInfo: Fitter placement operations ending: elapsed time is 00:00:05Info: Starting physical synthesis optimizations for speedInfo: Starting physical synthesis algorithm automatic asynchronous signal pipeliningInfo: Automatic asynchronous signal pipelining - Execution PhaseInfo: Pipelining signal |CII_Starter_USB_API|Reset_Delay:d0|oRESETInfo: Register reach: 25Warning: Automatic asynchronous signal pipelining is demoting global signal |CII_Starter_USB_API|Reset_Delay:d0|oRESET~clkctrlInfo: Inserted 5 registers on 3 stagesInfo: Physical synthesis algorithm automatic asynchronous signal pipelining completeInfo: Starting physical synthesis algorithm register retimingInfo: Physical synthesis algorithm register retiming complete: estimated slack improvement of 92 psInfo: Starting physical synthesis algorithm combinational resynthesis using boolean divisionInfo: Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 psInfo: Starting physical synthesis algorithm logic and register replicationInfo: Physical synthesis algorithm logic and register replication complete: estimated slack improvement of 0 psInfo: Starting physical synthesis algorithm fanout splittingInfo: Physical synthesis algorithm fanout splitting complete: estimated slack improvement of 0 psInfo: Physical synthesis optimizations for speed complete: elapsed cpu time is 00:00:43Info: Fitter routing operations beginningInfo: Average interconnect usage is 7% of the available device resourcesInfo: Peak interconnect usage is 12% of the available device resources in the region that extends from location X25_Y0 to location X37_Y13Info: Fitter routing operations ending: elapsed time is 00:00:06Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.Info: Optimizations that may affect the design's routability were skippedInfo: Optimizations that may affect the design's timing were skippedInfo: Started post-fitting delay annotationWarning: Found 256 output pins without output pin load capacitance assignmentInfo: Pin "HEX0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX2[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "HEX3[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDG[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "LEDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "UART_TXD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_LDQM" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_UDQM" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_CAS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_RAS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_CS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_BA_0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_BA_1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_CKE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_ADDR[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_RST_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_OE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_CE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_ADDR[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_UB_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_LB_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_WE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_CE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_OE_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SD_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "TDO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "I2C_SCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_HS" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_VS" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_R[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_R[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_R[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_R[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_G[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_G[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_G[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_G[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_B[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_B[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_B[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "VGA_B[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "AUD_ADCLRCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "AUD_DACLRCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "AUD_DACDAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "AUD_XCK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SD_DAT3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SD_CMD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "DRAM_DQ[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FL_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SRAM_DQ[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "SD_DAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "I2C_SDAT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "AUD_BCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[32]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[33]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[34]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_0[35]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[32]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[33]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[34]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "GPIO_1[35]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Delay annotation completed successfullyInfo: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.Warning: Following 76 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting resultsInfo: Pin SD_DAT3 has a permanently disabled output enableInfo: Pin SD_CMD has a permanently disabled output enableInfo: Pin SD_DAT has a permanently disabled output enableInfo: Pin AUD_BCLK has a permanently enabled output enableInfo: Pin GPIO_0[0] has a permanently disabled output enableInfo: Pin GPIO_0[1] has a permanently disabled output enableInfo: Pin GPIO_0[2] has a permanently disabled output enableInfo: Pin GPIO_0[3] has a permanently disabled output enableInfo: Pin GPIO_0[4] has a permanently disabled output enableInfo: Pin GPIO_0[5] has a permanently disabled output enableInfo: Pin GPIO_0[6] has a permanently disabled output enableInfo: Pin GPIO_0[7] has a permanently disabled output enableInfo: Pin GPIO_0[8] has a permanently disabled output enableInfo: Pin GPIO_0[9] has a permanently disabled output enableInfo: Pin GPIO_0[10] has a permanently disabled output enableInfo: Pin GPIO_0[11] has a permanently disabled output enableInfo: Pin GPIO_0[12] has a permanently disabled output enableInfo: Pin GPIO_0[13] has a permanently disabled output enableInfo: Pin GPIO_0[14] has a permanently disabled output enableInfo: Pin GPIO_0[15] has a permanently disabled output enableInfo: Pin GPIO_0[16] has a permanently disabled output enableInfo: Pin GPIO_0[17] has a permanently disabled output enableInfo: Pin GPIO_0[18] has a permanently disabled output enableInfo: Pin GPIO_0[19] has a permanently disabled output enableInfo: Pin GPIO_0[20] has a permanently disabled output enableInfo: Pin GPIO_0[21] has a permanently disabled output enableInfo: Pin GPIO_0[22] has a permanently disabled output enableInfo: Pin GPIO_0[23] has a permanently disabled output enableInfo: Pin GPIO_0[24] has a permanently disabled output enableInfo: Pin GPIO_0[25] has a permanently disabled output enableInfo: Pin GPIO_0[26] has a permanently disabled output enableInfo: Pin GPIO_0[27] has a permanently disabled output enableInfo: Pin GPIO_0[28] has a permanently disabled output enableInfo: Pin GPIO_0[29] has a permanently disabled output enableInfo: Pin GPIO_0[30] has a permanently disabled output enableInfo: Pin GPIO_0[31] has a permanently disabled output enableInfo: Pin GPIO_0[32] has a permanently disabled output enableInfo: Pin GPIO_0[33] has a permanently disabled output enableInfo: Pin GPIO_0[34] has a permanently disabled output enableInfo: Pin GPIO_0[35] has a permanently disabled output enableInfo: Pin GPIO_1[0] has a permanently disabled output enableInfo: Pin GPIO_1[1] has a permanently disabled output enableInfo: Pin GPIO_1[2] has a permanently disabled output enableInfo: Pin GPIO_1[3] has a permanently disabled output enableInfo: Pin GPIO_1[4] has a permanently disabled output enableInfo: Pin GPIO_1[5] has a permanently disabled output enableInfo: Pin GPIO_1[6] has a permanently disabled output enableInfo: Pin GPIO_1[7] has a permanently disabled output enableInfo: Pin GPIO_1[8] has a permanently disabled output enableInfo: Pin GPIO_1[9] has a permanently disabled output enableInfo: Pin GPIO_1[10] has a permanently disabled output enableInfo: Pin GPIO_1[11] has a permanently disabled output enableInfo: Pin GPIO_1[12] has a permanently disabled output enableInfo: Pin GPIO_1[13] has a permanently disabled output enableInfo: Pin GPIO_1[14] has a permanently disabled output enableInfo: Pin GPIO_1[15] has a permanently disabled output enableInfo: Pin GPIO_1[16] has a permanently disabled output enableInfo: Pin GPIO_1[17] has a permanently disabled output enableInfo: Pin GPIO_1[18] has a permanently disabled output enableInfo: Pin GPIO_1[19] has a permanently disabled output enableInfo: Pin GPIO_1[20] has a permanently disabled output enableInfo: Pin GPIO_1[21] has a permanently disabled output enableInfo: Pin GPIO_1[22] has a permanently disabled output enableInfo: Pin GPIO_1[23] has a permanently disabled output enableInfo: Pin GPIO_1[24] has a permanently disabled output enableInfo: Pin GPIO_1[25] has a permanently disabled output enableInfo: Pin GPIO_1[26] has a permanently disabled output enableInfo: Pin GPIO_1[27] has a permanently disabled output enableInfo: Pin GPIO_1[28] has a permanently disabled output enableInfo: Pin GPIO_1[29] has a permanently disabled output enableInfo: Pin GPIO_1[30] has a permanently disabled output enableInfo: Pin GPIO_1[31] has a permanently disabled output enableInfo: Pin GPIO_1[32] has a permanently disabled output enableInfo: Pin GPIO_1[33] has a permanently disabled output enableInfo: Pin GPIO_1[34] has a permanently disabled output enableInfo: Pin GPIO_1[35] has a permanently disabled output enableWarning: Following 81 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting resultsInfo: Pin UART_TXD has GND driving its datain portInfo: Pin FL_RST_N has VCC driving its datain portInfo: Pin SRAM_UB_N has GND driving its datain portInfo: Pin SRAM_LB_N has GND driving its datain portInfo: Pin SRAM_CE_N has GND driving its datain portInfo: Pin SD_CLK has GND driving its datain portInfo: Pin SD_DAT3 has VCC driving its datain portInfo: Pin SD_CMD has VCC driving its datain portInfo: Pin SD_DAT has VCC driving its datain portInfo: Pin GPIO_0[0] has VCC driving its datain portInfo: Pin GPIO_0[1] has VCC driving its datain portInfo: Pin GPIO_0[2] has VCC driving its datain portInfo: Pin GPIO_0[3] has VCC driving its datain portInfo: Pin GPIO_0[4] has VCC driving its datain portInfo: Pin GPIO_0[5] has VCC driving its datain portInfo: Pin GPIO_0[6] has VCC driving its datain portInfo: Pin GPIO_0[7] has VCC driving its datain portInfo: Pin GPIO_0[8] has VCC driving its datain portInfo: Pin GPIO_0[9] has VCC driving its datain portInfo: Pin GPIO_0[10] has VCC driving its datain portInfo: Pin GPIO_0[11] has VCC driving its datain portInfo: Pin GPIO_0[12] has VCC driving its datain portInfo: Pin GPIO_0[13] has VCC driving its datain portInfo: Pin GPIO_0[14] has VCC driving its datain portInfo: Pin GPIO_0[15] has VCC driving its datain portInfo: Pin GPIO_0[16] has VCC driving its datain portInfo: Pin GPIO_0[17] has VCC driving its datain portInfo: Pin GPIO_0[18] has VCC driving its datain portInfo: Pin GPIO_0[19] has VCC driving its datain portInfo: Pin GPIO_0[20] has VCC driving its datain portInfo: Pin GPIO_0[21] has VCC driving its datain portInfo: Pin GPIO_0[22] has VCC driving its datain portInfo: Pin GPIO_0[23] has VCC driving its datain portInfo: Pin GPIO_0[24] has VCC driving its datain portInfo: Pin GPIO_0[25] has VCC driving its datain portInfo: Pin GPIO_0[26] has VCC driving its datain portInfo: Pin GPIO_0[27] has VCC driving its datain portInfo: Pin GPIO_0[28] has VCC driving its datain portInfo: Pin GPIO_0[29] has VCC driving its datain portInfo: Pin GPIO_0[30] has VCC driving its datain portInfo: Pin GPIO_0[31] has VCC driving its datain portInfo: Pin GPIO_0[32] has VCC driving its datain portInfo: Pin GPIO_0[33] has VCC driving its datain portInfo: Pin GPIO_0[34] has VCC driving its datain portInfo: Pin GPIO_0[35] has VCC driving its datain portInfo: Pin GPIO_1[0] has VCC driving its datain portInfo: Pin GPIO_1[1] has VCC driving its datain portInfo: Pin GPIO_1[2] has VCC driving its datain portInfo: Pin GPIO_1[3] has VCC driving its datain portInfo: Pin GPIO_1[4] has VCC driving its datain portInfo: Pin GPIO_1[5] has VCC driving its datain portInfo: Pin GPIO_1[6] has VCC driving its datain portInfo: Pin GPIO_1[7] has VCC driving its datain portInfo: Pin GPIO_1[8] has VCC driving its datain portInfo: Pin GPIO_1[9] has VCC driving its datain portInfo: Pin GPIO_1[10] has VCC driving its datain portInfo: Pin GPIO_1[11] has VCC driving its datain portInfo: Pin GPIO_1[12] has VCC driving its datain portInfo: Pin GPIO_1[13] has VCC driving its datain portInfo: Pin GPIO_1[14] has VCC driving its datain portInfo: Pin GPIO_1[15] has VCC driving its datain portInfo: Pin GPIO_1[16] has VCC driving its datain portInfo: Pin GPIO_1[17] has VCC driving its datain portInfo: Pin GPIO_1[18] has VCC driving its datain portInfo: Pin GPIO_1[19] has VCC driving its datain portInfo: Pin GPIO_1[20] has VCC driving its datain portInfo: Pin GPIO_1[21] has VCC driving its datain portInfo: Pin GPIO_1[22] has VCC driving its datain portInfo: Pin GPIO_1[23] has VCC driving its datain portInfo: Pin GPIO_1[24] has VCC driving its datain portInfo: Pin GPIO_1[25] has VCC driving its datain portInfo: Pin GPIO_1[26] has VCC driving its datain portInfo: Pin GPIO_1[27] has VCC driving its datain portInfo: Pin GPIO_1[28] has VCC driving its datain portInfo: Pin GPIO_1[29] has VCC driving its datain portInfo: Pin GPIO_1[30] has VCC driving its datain portInfo: Pin GPIO_1[31] has VCC driving its datain portInfo: Pin GPIO_1[32] has VCC driving its datain portInfo: Pin GPIO_1[33] has VCC driving its datain portInfo: Pin GPIO_1[34] has VCC driving its datain portInfo: Pin GPIO_1[35] has VCC driving its datain portInfo: Following groups of pins have the same output enableInfo: Following pins have the same output enable: Multi_Sdram:u3|Sdram_Controller:u1|command:command1|OEInfo: Type bi-directional pin DRAM_DQ[2] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[9] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[0] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[7] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[15] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[6] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[14] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[5] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[13] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[4] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[12] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[3] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[11] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[10] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[1] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin DRAM_DQ[8] uses the 3.3-V LVTTL I/O standardInfo: Following pins have the same output enable: Multi_Flash:u2|Flash_Controller:u1|ST.READ (inverted)Info: Type bi-directional pin FL_DQ[2] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin FL_DQ[0] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin FL_DQ[7] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin FL_DQ[6] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin FL_DQ[5] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin FL_DQ[4] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin FL_DQ[3] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin FL_DQ[1] uses the 3.3-V LVTTL I/O standardInfo: Following pins have the same output enable: Multi_Sram:u6|SRAM_WE_N~3Info: Type bi-directional pin SRAM_DQ[10] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[1] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[8] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[7] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[15] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[6] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[14] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[5] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[13] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[4] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[12] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[3] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[11] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[2] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[9] uses the 3.3-V LVTTL I/O standardInfo: Type bi-directional pin SRAM_DQ[0] uses the 3.3-V LVTTL I/O standardInfo: Following pins have the same output enable: I2C_AV_Config:u10|I2C_Controller:u0|SDOInfo: Type bi-directional pin I2C_SDAT uses the 3.3-V LVTTL I/O standardWarning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.Info: Quartus II Fitter was successful. 0 errors, 60 warningsInfo: Peak virtual memory: 252 megabytesInfo: Processing ended: Sun Oct 11 12:25:00 2009Info: Elapsed time: 00:01:38Info: Total CPU time (on all processors): 00:01:31