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[/] [amber/] [trunk/] [hw/] [tools/] - Rev 20

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Last modification

  • Rev 20 2011-02-25 15:39:25 GMT
  • Author: csantifort
  • Log message:
    Added feature to A25 core to directly use a read value from the write back stage
    to reduce the stall to 1 cycle when there is a register conflict with the
    following instruction. This increases performance by about 3%.
Path Last modification Log RSS feed
[FOLDER] amber/ 20  4855d 01h csantifort View Log RSS feed
[NODE][FOLDER] branches/ 1  4919d 02h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4919d 02h root View Log RSS feed
[NODE][FOLDER] trunk/ 20  4855d 01h csantifort View Log RSS feed
[NODE][NODE][FOLDER] doc/ 20  4855d 01h csantifort View Log RSS feed
[NODE][NODE][FOLDER] hw/ 20  4855d 01h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] fpga/ 19  4855d 01h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 20  4855d 01h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tests/ 20  4855d 01h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tools/ 20  4855d 01h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] all.sh 20  4855d 01h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] get_timeout.sh 15  4861d 14h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] run.sh 17  4858d 23h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] set_timeout.sh 15  4861d 14h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] vlog/ 20  4855d 01h csantifort View Log RSS feed
[NODE][NODE][FOLDER] sw/ 15  4861d 14h csantifort View Log RSS feed

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