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[/] [minsoc/] [trunk/] [prj/] - Rev 108

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Last modification

  • Rev 108 2011-10-26 16:48:51 GMT
  • Author: rfajardo
  • Log message:
    Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

    Icarus Verilog and Altera synthesis are working as well. Job done!
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[NODE][FOLDER] tags/ 42  4837d 02h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  4611d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 105  4612d 07h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  4781d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  4647d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 108  4611d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  4656d 07h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 108  4611d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  4656d 07h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 96  4656d 18h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  4656d 07h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 104  4619d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  4661d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 104  4619d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 80  4680d 05h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 107  4612d 02h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 106  4612d 05h rfajardo View Log RSS feed

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