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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] - Rev 23
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Last modification
- Rev 23 2009-08-30 16:39:26 GMT
- Author: olivier.girard
- Log message:
- Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).