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https://opencores.org/ocsvn/spi/spi/trunk
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[/] [spi/] [trunk/] [rtl/] [verilog/] - Rev 10
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Last modification
- Rev 10 2003-05-26 10:56:27 GMT
- Author: simons
- Log message:
- Slave select signal generation bug fixed, default case added when reading registers, to avoid latches.