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https://opencores.org/ocsvn/xge_mac/xge_mac/trunk
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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] - Rev 21
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Last modification
- Rev 21 2012-11-23 22:01:26 GMT
- Author: antanguay
- Log message:
- Improvements for timing, adding alternate FIFO design using XIL define