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[/] [uart16550/] [tags/] [rel_2/] [sim/] - Rev 96
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Last modification
- Rev 96 2004-03-27 04:09:24 GMT
- Author: tadejm
- Log message:
- Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish.