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[/] [uart16550/] [tags/] [rel_4/] [bench/] - Rev 48
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Last modification
- Rev 48 2001-12-03 21:44:29 GMT
- Author: gorban
- Log message:
- Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.