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[/] [uart16550/] [tags/] [rel_4/] [bench/] - Rev 94
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Last modification
- Rev 94 2004-03-27 04:04:57 GMT
- Author: tadejm
- Log message:
- Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.