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https://opencores.org/ocsvn/uart_fifo_cpu_if_sv_testbench/uart_fifo_cpu_if_sv_testbench/trunk
Subversion Repositories uart_fifo_cpu_if_sv_testbench
[/] - Rev 3
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Last modification
- Rev 3 2011-01-03 21:12:44 GMT
- Author: andrewbridger
- Log message:
- Changed to send and receive least significant bit first.