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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu.v] - Rev 186

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186 root 5506d 06h /8051/trunk/rtl/verilog/oc8051_alu.v
185 root 5562d 07h /8051/trunk/rtl/verilog/oc8051_alu.v
179 add /* synopsys xx_case */ to case statments. simont 7641d 00h /8051/trunk/rtl/verilog/oc8051_alu.v
178 x replaced with 0. simont 7641d 02h /8051/trunk/rtl/verilog/oc8051_alu.v
171 fix bug in DA operation. simont 7663d 04h /8051/trunk/rtl/verilog/oc8051_alu.v
152 sub_result output added. simont 7669d 04h /8051/trunk/rtl/verilog/oc8051_alu.v
143 add wire sub_result, conect it to des_acc and des1. simont 7696d 09h /8051/trunk/rtl/verilog/oc8051_alu.v
139 add aditional alu destination to solve critical path. simont 7698d 05h /8051/trunk/rtl/verilog/oc8051_alu.v
133 fix bug in substraction. simont 7704d 13h /8051/trunk/rtl/verilog/oc8051_alu.v
132 change branch instruction execution (reduse needed clock periods). simont 7708d 04h /8051/trunk/rtl/verilog/oc8051_alu.v
123 fiz bug iv pcs operation. simont 7719d 07h /8051/trunk/rtl/verilog/oc8051_alu.v
82 replace some modules simont 7810d 07h /8051/trunk/rtl/verilog/oc8051_alu.v
46 prepared header simont 7915d 04h /8051/trunk/rtl/verilog/oc8051_alu.v
22 fix some bugs simont 7955d 02h /8051/trunk/rtl/verilog/oc8051_alu.v
11 des2_r removed simont 7960d 06h /8051/trunk/rtl/verilog/oc8051_alu.v
10 % replaced with ^ in uart; some minor improvements markom 7960d 12h /8051/trunk/rtl/verilog/oc8051_alu.v
8 some IDS optimizations markom 7962d 05h /8051/trunk/rtl/verilog/oc8051_alu.v
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 7962d 06h /8051/trunk/rtl/verilog/oc8051_alu.v
5 more linter corrections; 2 tests still fail markom 7962d 08h /8051/trunk/rtl/verilog/oc8051_alu.v
4 Code repaired to satisfy the linter; testbech fails markom 7962d 10h /8051/trunk/rtl/verilog/oc8051_alu.v
2 Initial CVS import simont 7978d 08h /8051/trunk/rtl/verilog/oc8051_alu.v

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