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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Rev 186

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186 root 5513d 08h /8051/trunk/rtl/verilog/oc8051_top.v
185 root 5569d 09h /8051/trunk/rtl/verilog/oc8051_top.v
181 Simulation reports added. simont 7648d 01h /8051/trunk/rtl/verilog/oc8051_top.v
174 ram modules added. simont 7659d 10h /8051/trunk/rtl/verilog/oc8051_top.v
172 BIST signals added. simont 7662d 09h /8051/trunk/rtl/verilog/oc8051_top.v
148 include "8051_defines" added. simont 7676d 06h /8051/trunk/rtl/verilog/oc8051_top.v
144 chsnge comp.des to des1 simont 7703d 11h /8051/trunk/rtl/verilog/oc8051_top.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7704d 13h /8051/trunk/rtl/verilog/oc8051_top.v
139 add aditional alu destination to solve critical path. simont 7705d 07h /8051/trunk/rtl/verilog/oc8051_top.v
134 fix bug in case execution of two data dependent instructions. simont 7711d 12h /8051/trunk/rtl/verilog/oc8051_top.v
132 change branch instruction execution (reduse needed clock periods). simont 7715d 06h /8051/trunk/rtl/verilog/oc8051_top.v
122 deifne OC8051_ROM added simont 7729d 13h /8051/trunk/rtl/verilog/oc8051_top.v
120 defines for pherypherals added simont 7730d 10h /8051/trunk/rtl/verilog/oc8051_top.v
118 change wr_sft to 2 bit wire. simont 7731d 07h /8051/trunk/rtl/verilog/oc8051_top.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7731d 07h /8051/trunk/rtl/verilog/oc8051_top.v
107 Include instruction cache. simont 7737d 04h /8051/trunk/rtl/verilog/oc8051_top.v
102 raname signals. simont 7738d 08h /8051/trunk/rtl/verilog/oc8051_top.v
82 replace some modules simont 7817d 09h /8051/trunk/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7886d 06h /8051/trunk/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7894d 08h /8051/trunk/rtl/verilog/oc8051_top.v
62 fix bugs in instruction interface simont 7899d 06h /8051/trunk/rtl/verilog/oc8051_top.v
54 cahnge interface to instruction rom simont 7905d 04h /8051/trunk/rtl/verilog/oc8051_top.v
46 prepared header simont 7922d 06h /8051/trunk/rtl/verilog/oc8051_top.v
37 added signals ack, stb and cyc simont 7949d 08h /8051/trunk/rtl/verilog/oc8051_top.v
28 remove syn signal simont 7960d 12h /8051/trunk/rtl/verilog/oc8051_top.v
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 7960d 14h /8051/trunk/rtl/verilog/oc8051_top.v
19 combinatorial loop removed simont 7963d 04h /8051/trunk/rtl/verilog/oc8051_top.v
17 fix some bugs simont 7966d 09h /8051/trunk/rtl/verilog/oc8051_top.v
12 des1_r in alu port list simont 7967d 08h /8051/trunk/rtl/verilog/oc8051_top.v
9 removed unused compare states markom 7969d 07h /8051/trunk/rtl/verilog/oc8051_top.v

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