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[/] [c16/] [trunk] - Rev 26

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Rev Log message Author Age Path
26 New directory structure. root 5576d 02h /c16/trunk
25 XOR bug fixed jsauermann 6634d 09h /trunk
24 no message jsauermann 6795d 07h /trunk
23 Fixed problem with wishbone wait-states jsauermann 6935d 06h /trunk
21 Changes for Xilinx Proj. Nav. 7.1.02i jsauermann 6935d 11h /trunk
19 FPGA Pin desription added. jsauermann 7131d 08h /trunk
18 Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires a fix in rtos.c as well		 jsauermann 7432d 07h /trunk
17 Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires a fix in rtos.c as well		 jsauermann 7432d 07h /trunk
16 Enable interrupts at start of each task.
This fix is required after a change in opcode_decoder.vhd.		 jsauermann 7432d 08h /trunk
15 sample ucf file jsauermann 7471d 11h /trunk
14 no message jsauermann 7479d 12h /trunk
13 bug in print_unsigned() fixed.
Now done as in rtos.c		 jsauermann 7522d 05h /trunk
12 Todo removed jsauermann 7551d 03h /trunk
11 First Version jsauermann 7551d 03h /trunk
10 Set top of stack of idle task to end of internal memory rather
than end of external memory (causing incorrect display of
100 % CPU load).		 jsauermann 7551d 05h /trunk
9 Made cpu_engine WISHBONE compliant.
(Somebody please validate it).		 jsauermann 7551d 05h /trunk
8 Initialization of compound auto variables added (was TODO) jsauermann 7558d 08h /trunk
7 Handle auto variable declarations in compound statements properly jsauermann 7559d 07h /trunk
6 New Target polled for testing compiler without the need to simulate interrupts jsauermann 7559d 07h /trunk
5 Initial version jsauermann 7560d 04h /trunk
4 Documentation finalized jsauermann 7560d 08h /trunk
2 no message jsauermann 7563d 04h /trunk
1 Standard project directories initialized by cvs2svn. 7563d 04h /trunk

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