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[/] [uart16550/] [tags/] [asyst_3/] - Rev 106

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106 New directory structure. root 5573d 11h /uart16550/tags/asyst_3
77 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 8149d 05h /tags/asyst_3
75 Endian define added. Big Byte Endian is selected by default. mohor 8149d 05h /trunk
74 tf_overrun signal was disabled since it was not used gorban 8154d 06h /trunk
73 major bug in 32-bit mode that prevented register access fixed. gorban 8161d 05h /trunk
72 UART PHY added. Files are fully operational, working on HW. mohor 8174d 13h /trunk
71 Removed confusing comment gorban 8186d 01h /trunk
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8191d 10h /trunk
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8200d 01h /trunk
68 lsr[7] was not showing overrun errors. mohor 8203d 08h /trunk
67 Missing declaration of rf_push_q fixed. mohor 8210d 08h /trunk
66 rx push changed to be only one cycle wide. mohor 8210d 08h /trunk
65 Warnings fixed (unused signals removed). mohor 8211d 13h /trunk
64 Warnings cleared. mohor 8211d 14h /trunk
63 Synplicity was having troubles with the comment. mohor 8211d 14h /trunk
62 Bug that was entered in the last update fixed (rx state machine). mohor 8212d 13h /trunk
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8213d 07h /trunk
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8213d 11h /trunk
59 MSR register fixed. mohor 8216d 08h /trunk
58 After reset modem status register MSR should be reset. mohor 8216d 11h /trunk
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8217d 11h /trunk
56 thre irq should be cleared only when being source of interrupt. mohor 8217d 11h /trunk
55 some synthesis bugs fixed gorban 8217d 23h /trunk
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8218d 12h /trunk
53 Scratch register define added. mohor 8219d 13h /trunk
52 Scratch register added gorban 8220d 02h /trunk
51 Igor fixed break condition bugs gorban 8220d 02h /trunk
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8224d 07h /trunk
49 committed the debug interface file gorban 8226d 00h /trunk
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8227d 00h /trunk

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