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[/] [uart16550/] [tags/] [rel_3/] - Rev 106

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Rev	Log message	Author	Age	Path
106	New directory structure.	root	5573d 08h	/uart16550/tags/rel_3
102	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7327d 05h	/tags/rel_3
101	Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode.	tadejm	7327d 05h	/trunk
100	Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs.	tadejm	7327d 06h	/trunk
99	Added synchronizer flops for RX input.	tadejm	7327d 06h	/trunk
98	Added to synchronize RX input to Wishbone clock.	tadejm	7327d 06h	/trunk
96	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish.	tadejm	7382d 14h	/trunk
95	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish.	tadejm	7382d 14h	/trunk
94	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7382d 14h	/trunk
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7382d 14h	/trunk
92	This is revision 1.4, revision 1.5 was put there by mistake.	simons	7496d 07h	/trunk
91	Removed files due to new complete testbench.	tadejm	7496d 22h	/trunk
90	Add Flextronics header	avisha	7499d 05h	/trunk
89	adjusted comment + define	dries	7579d 10h	/trunk
88	added clearing the receiver fifo statuses on resets	gorban	7641d 23h	/trunk
87	This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.	gorban	7672d 01h	/trunk
86	restored include for uart_defines.v in uart_test.v	gorban	7942d 05h	/trunk
85	Updated documentation to include latest changes.	gorban	7975d 21h	/trunk
84	The uart_defines.v file is included again in sources.	gorban	7988d 20h	/trunk
83	Reverted to include uart_defines.v file in other files again.	gorban	7988d 20h	/trunk
82	Updated to work with latest core.	gorban	7995d 18h	/trunk
81	Added lastest additions.	gorban	7995d 19h	/trunk
80	Remove uart_fifo.v because it is replaced by other 2 files.	gorban	7995d 19h	/trunk
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	7995d 19h	/trunk
75	Endian define added. Big Byte Endian is selected by default.	mohor	8149d 01h	/trunk
74	tf_overrun signal was disabled since it was not used	gorban	8154d 02h	/trunk
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8161d 01h	/trunk
72	UART PHY added. Files are fully operational, working on HW.	mohor	8174d 09h	/trunk
71	Removed confusing comment	gorban	8185d 21h	/trunk
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8191d 06h	/trunk

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[/] [uart16550/] [tags/] [rel_3/] - Rev 106

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