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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

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[/] [virtex7_pcie_dma/] - Rev 47

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47 Deleted all files, the repository was moved to Nikhef Gitlab, files will come back to OpenCores when it supports git. fransschreuder 1003d 16h /virtex7_pcie_dma
46 New Vivado version, changed regmap clock, added byte enable to regmap
* Updated wupper for Vivado 2018.1
* Byte enable on registermap is now supported
* Fixed i2c mux reset (inversion) on VC709 board
* Regmap is now running on 25 MHz for better timing, this was 41.6 MHz
* registers can now be disabled at build time using the generate statement in the .yaml file
fransschreuder 1850d 14h /virtex7_pcie_dma
45 Fixed duplicate driver and Vivado 2018.1 PCIe core fransschreuder 1874d 22h /virtex7_pcie_dma
44 EDITED: added image size aborga 1962d 14h /virtex7_pcie_dma
43 ADDED: README.md to be parsed by the OC project page aborga 1962d 19h /virtex7_pcie_dma
42 Added filter in wuppercodegen in order to generate 2d arrays of registers fransschreuder 2307d 19h /virtex7_pcie_dma
41 Added brief description of Wishbone broel 2407d 18h /virtex7_pcie_dma
40 Updated comment header for syscon. broel 2407d 20h /virtex7_pcie_dma
39 Added Wishbone bus to Wupper plus a Wishbone memory as an example. broel 2411d 15h /virtex7_pcie_dma
38 Fixed include of stdint.h broel 2419d 21h /virtex7_pcie_dma
37 * Added WupperCodeGen, a tool to generate the registermap vhdl, c++ and latex doc from a single .YAML file
* Fixed bug: crash when polling enable bits while transferring DMA in two directions at the same time
* Code cleanup
* Updated documentation with WupperCodeGen
fransschreuder 2420d 14h /virtex7_pcie_dma
36 Updated documentation fransschreuder 2755d 15h /virtex7_pcie_dma
35 FIXED:
* PCIe lock when reading registers on a high frequency
* Added threshold registers for Prog Full of the FromHost fifo
* Code cleanup
fransschreuder 2809d 19h /virtex7_pcie_dma
34 FIXED:
* Wrong TLP length reported on register writes
* Two simultaneous interrupts were not handled
* XADC wizard for ultrascale devices

Added:
* Added voltage (int, aux, bram) readout on XADC wizards
fransschreuder 2915d 14h /virtex7_pcie_dma
33 ADDED:
-- supportedtools.tex, again to test the OC repo
aborga 2960d 13h /virtex7_pcie_dma
32 MODIFIED:
-- minor things just to test OC svn repo
aborga 2960d 13h /virtex7_pcie_dma
31 Added example application documentation. oussamak 3054d 15h /virtex7_pcie_dma
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools
oussamak 3054d 16h /virtex7_pcie_dma
29 Improved application to reflect both up and down transfers fransschreuder 3096d 13h /virtex7_pcie_dma
28 Added registermap reset fransschreuder 3096d 16h /virtex7_pcie_dma
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming
fransschreuder 3096d 18h /virtex7_pcie_dma
26 Added sys_clk constraint fransschreuder 3096d 21h /virtex7_pcie_dma
25 Added scripts and constraints for KCU105 fransschreuder 3096d 21h /virtex7_pcie_dma
24 Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105
fransschreuder 3097d 14h /virtex7_pcie_dma
23 Fixed reset of application registers fransschreuder 3154d 20h /virtex7_pcie_dma
22 Added dma_soft_reset to trigger register resets fransschreuder 3160d 20h /virtex7_pcie_dma
21 Fixed BUG http://opencores.org/bug,view,2562 fransschreuder 3169d 17h /virtex7_pcie_dma
20 Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size
fransschreuder 3183d 16h /virtex7_pcie_dma
19 * driver/README updated oussamak 3189d 17h /virtex7_pcie_dma
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register
oussamak 3189d 19h /virtex7_pcie_dma

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