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Subversion Repositories axi4_tlm_bfm

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Rev Log message Author Age Path
39 Deprecated symbolsPerTransfer and outstandingTransactions; replaced with lastTransaction. Fixed small bug in BFM; tData and tValid should be valid even for the last transaction. daniel.kho 3709d 16h /
38 Added coverage-driven randomisation to tester. daniel.kho 3709d 16h /
37 Refactored nReset to reset for real hardware. daniel.kho 3729d 06h /
36 Added missing pkg-types.vhdl file for simulation. daniel.kho 3756d 05h /
35 More fixes to Windows script. daniel.kho 3761d 15h /
34 Added double-quotes for Windows script. daniel.kho 3761d 16h /
33 Removed semicolons for Windows script. daniel.kho 3761d 16h /
32 Added compile+simulate script for Windows. daniel.kho 3761d 16h /
31 Added initial Xilinx Vivado synthesis scripts and constraints. daniel.kho 3775d 14h /
30 Refactored synthesis scripts. daniel.kho 3775d 14h /
29 Updated simulation scripts. daniel.kho 3775d 14h /
28 Temporarily remove simulation folder. daniel.kho 3775d 14h /
27 Updated simulation scripts. daniel.kho 3775d 14h /
26 Refactored simulation folders. daniel.kho 3775d 15h /
25 Refactored folders. daniel.kho 3775d 15h /
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3775d 15h /
23 Added top-level user example used in technical paper. daniel.kho 3783d 09h /
22 Added pin assignments for BeMicro kit. Added demo top-level used in technical paper. daniel.kho 3783d 09h /
21 Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. daniel.kho 3786d 11h /
20 Updated simulation scripts. daniel.kho 3786d 11h /
19 Updated synthesis constraints and scripts. daniel.kho 3786d 11h /
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3786d 12h /
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3786d 12h /
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3889d 08h /
15 [minor]: cleaned up sources. daniel.kho 3891d 15h /
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3900d 05h /
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3900d 10h /
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3909d 14h /
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3911d 08h /
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 3915d 08h /

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