URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

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Rev	Log message	Author	Age	Path
40	branches/singleSymbol: Updating testcases in TestRioSerial for fully synchronous RioSerial and correcting some bugs.	magro732	3505d 19h	/
39	branches/singleSymbol: Backup-checkin (not compiling) of new RioWbBridge with 64-bit Wishbone interface.	magro732	3512d 06h	/
38	RioLogicalCommon has working Maintenance-packet parsing. TestRioLogicalCommon has test cases for all Maintenance request packets.	magro732	3532d 11h	/
37	singleSymbol: Correcting compiler errors and misc minor errors.	magro732	3541d 06h	/
36	singleSymbol: Adding testbench for RioLogicalCommon.	magro732	3548d 06h	/
35	Temporary checkin of new synchronous RioSerial. Does not work yet. Temporary checkin of RioLogicalCommon. Does not work yet.	magro732	3551d 11h	/
34	Adding first version of logical egress.	magro732	3555d 05h	/
33	Adding common logical layer module.	magro732	3556d 10h	/
32	branches/singleSymbol Adding a wait-state to only insert one control-symbol into an outbound packet.	magro732	3559d 14h	/
31	Fixing compiler errors. Adding support for inserting control-symbols from receiver into frames.	magro732	3561d 14h	/
30	Changing name tags/1.0.1 to tags/1.0.1-release.	magro732	3561d 16h	/
29	Fixed bug in RioSwitch internal Wishbone interconnects.	magro732	3561d 17h	/
28	Correcting bug in RioSwitch.vhd internal Wishbone interconnect. Modifying an existing test case in TestRioSwitch.vhd to provoke the error.	magro732	3561d 17h	/
27	Adding missing code to single-symbol pipelined transmitter. Not tested nor copiled.	magro732	3563d 05h	/
26	Temporary checkin of parallelSymbols branch. It does not work yet.	magro732	3723d 16h	/
25	Correcting compiler errors in TestRioPcsUart.vhd	magro732	3730d 10h	/
24	Changing errornous use statement.	magro732	3730d 11h	/
23	Tagging alpha release 2.0.0.	magro732	3847d 04h	/
22	Tagging release 1.0.0.	magro732	3847d 04h	/
21	Branching of a single symbol version of the new RioSerial.	magro732	3847d 04h	/
20	Adding software C-stack and matching VHDL modules.	magro732	3912d 07h	/
19	Removing synthesis warnings.	magro732	3937d 06h	/
18	Making RioSerial entity the same as before+minor fixes.	magro732	3938d 05h	/
17	Removing latch and improving timing.	magro732	3939d 05h	/
16	Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing.	magro732	3939d 06h	/
15	All testcases are ok. Still needs some tweeks though.	magro732	3943d 07h	/
14	Most issues solved, testbench issues remains.	magro732	3946d 06h	/
13	Timeouts are working.	magro732	3949d 07h	/
12	Backup of recent work, debugging new RioSerial.	magro732	3960d 05h	/
11	Receiver ready, transmitter is compiling.	magro732	3960d 06h	/

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