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URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

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Rev Log message Author Age Path
151 Started to include generic VHDL description of memories. jlechner 5220d 18h /
150 Added old uploaded documents to new repository. root 5556d 22h /
149 Added old uploaded documents to new repository. root 5557d 05h /
148 New directory structure. root 5557d 05h /
147 - Updated to use current example. cwalter 6331d 13h /
146 - Changed to compile UART example. cwalter 6331d 15h /
145 - Added more VHDL files to project. cwalter 6331d 15h /
144 - IF stage now uses autogenerated VHDL files. cwalter 6331d 15h /
143 - Added more complex UART example. cwalter 6331d 15h /
142 - Added gap between characters sent and changed last character to CR. cwalter 6331d 15h /
141 - Added delay between characters. cwalter 6331d 16h /
140 - Test bench for RISE with UART. cwalter 6331d 16h /
139 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6331d 16h /
138 - Fixed binary to VHDL converter. cwalter 6331d 17h /
137 - Added binary to VHDL converter. cwalter 6331d 17h /
136 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6331d 17h /
135 uart_address_0 was a latch -> changed ustadler 6332d 13h /
134 Added second test program for testing uart. jlechner 6332d 13h /
133 - Fixed bug with ST opcodes. cwalter 6332d 15h /
132 Added test program for testing uart. jlechner 6332d 15h /
131 Changed high active resets to low active ones. jlechner 6332d 15h /
130 Removed obsolete line jlechner 6332d 15h /
129 Sample assembler program for accessing uart jlechner 6332d 16h /
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.		 jlechner 6332d 16h /
127 Changed high active resets to low active ones. jlechner 6332d 16h /
126 Added constant for cpu frequency (needed for UART) trinklhar 6332d 22h /
125 Fixed vhdl bugs trinklhar 6332d 22h /
124 Assigned UART signals to ports on top-level entity trinklhar 6332d 22h /
123 Removed UART again trinklhar 6332d 23h /
122 Removed UART again again trinklhar 6332d 23h /

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