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Rev Log message Author Age Path
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4209d 00h /
20 Updates for Xilinx synthesis antanguay 4498d 18h /
19 Updates for 32/64 bit systems antanguay 4673d 19h /
18 Updates for linux 32-bit antanguay 4674d 16h /
17 Fixed deprecated SystemC warnings antanguay 4677d 00h /
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4677d 06h /
15 Updated for Verilator 3.813 antanguay 4696d 06h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5285d 01h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5285d 01h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5285d 02h /
11 Fixed clock crossing antanguay 5390d 23h /
10 Added details to spec antanguay 5488d 18h /
9 Added old uploaded documents to new repository. root 5563d 05h /
8 Added old uploaded documents to new repository. root 5563d 11h /
7 New directory structure. root 5563d 11h /
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5839d 19h /
5 Fixed compilation antanguay 5845d 19h /
4 Created antanguay 5845d 22h /
3 This commit was manufactured by cvs2svn to create tag 'initial'. 5845d 23h /
2 Initial revision antanguay 5845d 23h /
1 Standard project directories initialized by cvs2svn. 5845d 23h /

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