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Rev Log message Author Age Path
161 New directory structure. root 5563d 22h /can/tags/rel_16/
122 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7583d 11h /tags/rel_16/
118 Artisan RAM fixed (when not using BIST). mohor 7592d 08h /trunk/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7592d 08h /trunk/
115 Artisan ram instances added. simons 7598d 02h /trunk/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7625d 03h /trunk/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7627d 03h /trunk/
110 Fixed according to the linter. mohor 7627d 03h /trunk/
109 Fixed according to the linter. mohor 7627d 04h /trunk/
108 Fixed according to the linter. mohor 7627d 04h /trunk/
107 Fixed according to the linter. mohor 7627d 05h /trunk/
106 Unused signal removed. mohor 7633d 03h /trunk/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7633d 16h /trunk/
102 Little fixes (to fix warnings). mohor 7636d 07h /trunk/
100 Synchronization changed. mohor 7640d 09h /trunk/
99 PCI_BIST replaced with CAN_BIST. mohor 7640d 09h /trunk/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7645d 20h /trunk/
95 Virtual silicon ram instances added. simons 7645d 21h /trunk/
93 synthesis full_case parallel_case fixed. mohor 7651d 08h /trunk/
92 clkout is clk/2 after the reset. mohor 7651d 17h /trunk/
90 paralel_case and full_case compiler directives added to case statements. mohor 7652d 06h /trunk/
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7653d 03h /trunk/
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.		 mohor 7653d 04h /trunk/
85 Typo fixed. mohor 7654d 19h /trunk/
84 clk_cnt reduced from [8:0] to [6:0]. mohor 7656d 02h /trunk/
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7656d 03h /trunk/
82 Removed few signals. mohor 7656d 04h /trunk/
81 "chip select" signal cs_can_i is used only when not using WISHBONE
interface.		 mohor 7656d 04h /trunk/
80 Form error was detected when stuff bit occured at the end of crc. mohor 7656d 04h /trunk/
79 Bit stuffing corrected when stuffing comes at the end of the crc. tadejm 7657d 04h /trunk/

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