OpenCores
URL https://opencores.org/ocsvn/light52/light52/trunk

Subversion Repositories light52

[/] [light52/] - Rev 26

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
26 Changed the VHDL simulation logging code to match the SW simulator.
The JBC ACC.x instruction is a special case that needs a tiny hack...
Note this affects only the simulation test bench, not the RTL!		 ja_rd 3836d 02h /light52/
25 Pre-generated object code packages updated with new test bench. ja_rd 3836d 02h /light52/
24 Basic CPU test bench modified to catch previously undetected bug in CLR BIT. Still too weak though... ja_rd 3836d 02h /light52/
23 Fixed CLR.bit when ACC was the target.
Implemented solution suggested by Stephane Bouyat, worked like a charm!		 ja_rd 3836d 02h /light52/
22 Fixed comments in object code package generation script.
The comments were awfully wrong -- leftover from another project, actually.		 ja_rd 4127d 05h /light52/
21 ja_rd 4142d 10h /light52/
20 ja_rd 4142d 10h /light52/
19 Refactor: interrupts made 100% compatible to original:
IRQ priority logic implemented as in original MCS51.
Register IP implemented.
Interrupt mini-testbench code updated accordingly.		 ja_rd 4142d 10h /light52/
18 Refactor: interrupts made 100% compatible to original:
IRQ priority logic implemented as in original MCS51.
Register IP implemented.
Interrupt mini-testbench code updated accordingly.		 ja_rd 4142d 10h /light52/
17 Refactor: interrupts made 100% compatible to original:
IRQ priority logic implemented as in original MCS51.
Register IP implemented.
Interrupt mini-testbench code updated accordingly.		 ja_rd 4142d 10h /light52/
16 Test bench modified: now tests IRAM and SFR addresses when testing direct mode instructions (instead of only IRAM). ja_rd 4144d 07h /light52/
15 Test bench modified: now tests IRAM and SFR addresses when testing direct mode instructions (instead of only IRAM). ja_rd 4148d 04h /light52/
14 BUG FIX: <DJNZ dir, rel> didn't work when addressing an SFR.
Signal direct_addressing fixed.		 ja_rd 4148d 10h /light52/
13 BUG FIX: <DJNZ dir, rel> was tested only with IRAM addresses.
Now it's tested with an SFR too.
The test package has been fixed too with a XRAM configuration suitable for the test bench (it was zero).		 ja_rd 4148d 10h /light52/
12 BUG FIX: The build script did not configure XDATA space properly.
XDATA size was zero, which made the HW tests fail.		 ja_rd 4148d 13h /light52/
11 Removed old 'demos' directory. These files are now in the 'boards' directory. ja_rd 4210d 12h /light52/
10 Updated 'quickstart' to reflect new organization of demo directory. ja_rd 4210d 12h /light52/
9 Fixed quartus-2 project file -- replaced absolute output path with relative path. ja_rd 4210d 13h /light52/
8 Added support to build demos on another board: Avnet's Spartan-3A Evaluation Board. ja_rd 4213d 04h /light52/
7 Removed obsolete comment from core include file. ja_rd 4213d 05h /light52/
6 Added a 'LED blinker' program to try the core on boards with no RS232 connector. ja_rd 4213d 05h /light52/
5 Committed source and project files for Dhrystone demo on Terasic's DE-1 board. ja_rd 4214d 14h /light52/
4 Committed support tools including simulator. ja_rd 4214d 16h /light52/
3 Committed documentation and example programs. ja_rd 4214d 16h /light52/
2 Full VHDL sources and Modelsim scripts.
This is a migration of an existing project.		 ja_rd 4214d 16h /light52/
1 The project and the structure was created root 4214d 16h /light52/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.