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[/] [rio/] - Rev 49

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Rev Log message Author Age Path
49 Moving packet generation API from riostack.c to new file riopacket.c.
The riostack.c is now transparent to all packets and does not answer on its own to maintenance packets. That now has to be handled in the user-written code that instantiates the riostack.
Moving all regression tests into new files test_riostack.c and test_riopacket.c.		 magro732 3428d 18h /rio/
48 Moving all packet parsing modules into RioLogicalPackets.vhd.
Optimizing RioLogicalCommon.vhd interface and implementation.
Updating RioLogicalPackets.vhd to support the change in the RioLogicalCommon.vhd interface.
Moving simulation specific code from RioCommon.vhd to TestPortPackage.vhd.		 magro732 3434d 00h /rio/
47 Moving common component declarations into RioCommon.vhd.
Fixing RioSwitch to support full sized maintenance packets.
Fixing RioLogicalMaintenance to work with all sizes and minor interface change.
Fixing packet return port bug in RioSwitch.
Adding support for all maintenance packets into RioLogicalPackets.
Moving TestPorts to seperate file and changing their interface to be able to use generically.
Using TestPorts in TestRioSwitch.		 magro732 3467d 17h /rio/
46 Updating RioSwitch maintenance port to support all-sized maintenance packets.
The new maintenance port is easier to maintain and to add portWrite-support to.
Updating RioLogicalMaintenance to not contain the packet handlers.
Updating RioWbBridge to use the updated RioLogicalMaintenance interface.
Moving some component declarations to RioCommon.vhd.		 magro732 3470d 22h /rio/
45 Working RioWbBridge with 64-bit Wishbone interface.
Testcases for MAINTENANCE, NREAD, NWRITE/NWRITER.		 magro732 3489d 17h /rio/
44 Adding testcases for NREAD in TestRioWbBridge.
Correcting bugs in RioWbBridge and RioLogicalCommon.		 magro732 3495d 13h /rio/
43 Removing singleSymbol-branch. magro732 3500d 00h /rio/
42 Adding testbench for RioWbBridge.vhd. Not tested yet. magro732 3502d 10h /rio/
41 Changing name branches/singelSymbol->branches/2.0.0-development magro732 3505d 23h /rio/
40 branches/singleSymbol: Updating testcases in TestRioSerial for fully synchronous RioSerial and correcting some bugs. magro732 3505d 23h /rio/
39 branches/singleSymbol: Backup-checkin (not compiling) of new RioWbBridge with 64-bit Wishbone interface. magro732 3512d 10h /rio/
38 RioLogicalCommon has working Maintenance-packet parsing.
TestRioLogicalCommon has test cases for all Maintenance request packets.		 magro732 3532d 16h /rio/
37 singleSymbol: Correcting compiler errors and misc minor errors. magro732 3541d 10h /rio/
36 singleSymbol: Adding testbench for RioLogicalCommon. magro732 3548d 10h /rio/
35 Temporary checkin of new synchronous RioSerial. Does not work yet.
Temporary checkin of RioLogicalCommon. Does not work yet.		 magro732 3551d 15h /rio/
34 Adding first version of logical egress. magro732 3555d 10h /rio/
33 Adding common logical layer module. magro732 3556d 14h /rio/
32 branches/singleSymbol
Adding a wait-state to only insert one control-symbol into an outbound packet.		 magro732 3559d 18h /rio/
31 Fixing compiler errors.
Adding support for inserting control-symbols from receiver into frames.		 magro732 3561d 19h /rio/
30 Changing name tags/1.0.1 to tags/1.0.1-release. magro732 3561d 20h /rio/
29 Fixed bug in RioSwitch internal Wishbone interconnects. magro732 3561d 22h /rio/
28 Correcting bug in RioSwitch.vhd internal Wishbone interconnect.
Modifying an existing test case in TestRioSwitch.vhd to provoke the error.		 magro732 3561d 22h /rio/
27 Adding missing code to single-symbol pipelined transmitter. Not tested nor copiled. magro732 3563d 09h /rio/
26 Temporary checkin of parallelSymbols branch. It does not work yet. magro732 3723d 21h /rio/
25 Correcting compiler errors in TestRioPcsUart.vhd magro732 3730d 15h /rio/
24 Changing errornous use statement. magro732 3730d 15h /rio/
23 Tagging alpha release 2.0.0. magro732 3847d 08h /rio/
22 Tagging release 1.0.0. magro732 3847d 09h /rio/
21 Branching of a single symbol version of the new RioSerial. magro732 3847d 09h /rio/
20 Adding software C-stack and matching VHDL modules. magro732 3912d 11h /rio/

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