OpenCores
URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] - Rev 40

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
40 Updated comment header for syscon. broel 2407d 18h /virtex7_pcie_dma/
39 Added Wishbone bus to Wupper plus a Wishbone memory as an example. broel 2411d 12h /virtex7_pcie_dma/
38 Fixed include of stdint.h broel 2419d 19h /virtex7_pcie_dma/
37 * Added WupperCodeGen, a tool to generate the registermap vhdl, c++ and latex doc from a single .YAML file
* Fixed bug: crash when polling enable bits while transferring DMA in two directions at the same time
* Code cleanup
* Updated documentation with WupperCodeGen		 fransschreuder 2420d 12h /virtex7_pcie_dma/
36 Updated documentation fransschreuder 2755d 12h /virtex7_pcie_dma/
35 FIXED:
* PCIe lock when reading registers on a high frequency
* Added threshold registers for Prog Full of the FromHost fifo
* Code cleanup		 fransschreuder 2809d 17h /virtex7_pcie_dma/
34 FIXED:
* Wrong TLP length reported on register writes
* Two simultaneous interrupts were not handled
* XADC wizard for ultrascale devices

Added:
* Added voltage (int, aux, bram) readout on XADC wizards		 fransschreuder 2915d 12h /virtex7_pcie_dma/
33 ADDED:
-- supportedtools.tex, again to test the OC repo		 aborga 2960d 11h /virtex7_pcie_dma/
32 MODIFIED:
-- minor things just to test OC svn repo		 aborga 2960d 11h /virtex7_pcie_dma/
31 Added example application documentation. oussamak 3054d 13h /virtex7_pcie_dma/
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools		 oussamak 3054d 13h /virtex7_pcie_dma/
29 Improved application to reflect both up and down transfers fransschreuder 3096d 11h /virtex7_pcie_dma/
28 Added registermap reset fransschreuder 3096d 13h /virtex7_pcie_dma/
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming		 fransschreuder 3096d 16h /virtex7_pcie_dma/
26 Added sys_clk constraint fransschreuder 3096d 18h /virtex7_pcie_dma/
25 Added scripts and constraints for KCU105 fransschreuder 3096d 18h /virtex7_pcie_dma/
24 Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105		 fransschreuder 3097d 12h /virtex7_pcie_dma/
23 Fixed reset of application registers fransschreuder 3154d 18h /virtex7_pcie_dma/
22 Added dma_soft_reset to trigger register resets fransschreuder 3160d 17h /virtex7_pcie_dma/
21 Fixed BUG http://opencores.org/bug,view,2562 fransschreuder 3169d 14h /virtex7_pcie_dma/
20 Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size		 fransschreuder 3183d 13h /virtex7_pcie_dma/
19 * driver/README updated oussamak 3189d 15h /virtex7_pcie_dma/
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register		 oussamak 3189d 17h /virtex7_pcie_dma/
17 Changed name of toplevel, to make tree consistent oussamak 3203d 19h /virtex7_pcie_dma/
16 MODIFED:
-- top level name to wupper_oc (including scripts)		 aborga 3253d 13h /virtex7_pcie_dma/
15 MODIFIED:
-- Renamed core to Wupper (vhdl files)
-- Changed width of interrupt enable to number_of_interrupts		 fransschreuder 3253d 14h /virtex7_pcie_dma/
14 RENAMED:
-- simulation folder		 aborga 3253d 15h /virtex7_pcie_dma/
13 RENAMED:
-- script		 aborga 3253d 15h /virtex7_pcie_dma/
12 Fixed http://opencores.org/bug,view,2524 fransschreuder 3328d 15h /virtex7_pcie_dma/
11 MODIFIED:
-- updated documentation		 aborga 3341d 13h /virtex7_pcie_dma/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.