URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

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Rev	Log message	Author	Age	Path
155	add aditional tests.	simont	7674d 20h	/
154	File name fixed.	simont	7675d 15h	/
153	`ifdef added.	simont	7676d 14h	/
152	sub_result output added.	simont	7676d 14h	/
151	remove pc_r register.	simont	7676d 14h	/
150	fix some bugs.	simont	7676d 14h	/
149	pipelined acces to axternal instruction interface added.	simont	7676d 14h	/
148	include "8051_defines" added.	simont	7676d 15h	/
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7698d 15h	/
146	fix bug in movc intruction.	simont	7698d 15h	/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7703d 19h	/
144	chsnge comp.des to des1	simont	7703d 19h	/
143	add wire sub_result, conect it to des_acc and des1.	simont	7703d 19h	/
142	optimize state machine.	simont	7704d 20h	/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7704d 22h	/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7704d 22h	/
139	add aditional alu destination to solve critical path.	simont	7705d 16h	/
138	Change buffering to save one clock per instruction.	simont	7705d 16h	/
137	change to fit xrom.	simont	7705d 21h	/
136	registering outputs.	simont	7705d 21h	/
135	prepared start of receiving if ren is not active.	simont	7711d 20h	/
134	fix bug in case execution of two data dependent instructions.	simont	7711d 20h	/
133	fix bug in substraction.	simont	7711d 23h	/
132	change branch instruction execution (reduse needed clock periods).	simont	7715d 14h	/
131	prepare programs for new timing.	simont	7715d 14h	/
130	prepared programs for new timing.	simont	7715d 14h	/
129	updated...	simont	7715d 14h	/
128	chance idat_ir to 24 bit wide	simont	7724d 21h	/
127	fix bug (cyc_o and stb_o)	simont	7724d 22h	/
126	define OC8051_XILINX_RAMB added	simont	7724d 22h	/

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Subversion Repositories 8051

[/] - Rev 155

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