URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 78

Rev	Log message	Author	Age	Path
78	alu with registered outputs	simont	7877d 04h	/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7886d 01h	/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7886d 01h	/
75	initial import	simont	7886d 01h	/
74	add module oc8051_wb_iinterface	simont	7894d 02h	/
73	initial import	simont	7894d 02h	/
72	fix bug in interface to external data ram	simont	7894d 04h	/
71	add cache	simont	7898d 03h	/
70	initial import	simont	7898d 03h	/
69	add parameters	simont	7898d 05h	/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7898d 05h	/
67	add parameters for instruction cache	simont	7898d 05h	/
66	added xrom_test	simont	7899d 02h	/
65	add oc8051_icache and oc8051_cache_ram	simont	7899d 02h	/
64	signal es_int=1'b0	simont	7899d 02h	/
63	initial import	simont	7899d 02h	/
62	fix bugs in instruction interface	simont	7899d 02h	/
61	fix bug	simont	7900d 04h	/
60	initial inport	simont	7901d 05h	/
59	add external rom	simont	7905d 00h	/
58	add external rom testing	simont	7905d 00h	/
57	add module oc8051_xrom	simont	7905d 00h	/
56	initial CVS input	simont	7905d 00h	/
55	added parameter DELAY	simont	7905d 00h	/
54	cahnge interface to instruction rom	simont	7905d 00h	/
53	initial CVS inport	simont	7905d 00h	/
52	fix bugs	simont	7905d 00h	/
51	fix bugs	simont	7907d 05h	/
50	fix bugs	simont	7907d 06h	/
49	verification added	simont	7914d 05h	/