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21 Fix overrun and underrun interrupts bug

The overrun and underrun did not have any logic for
resetting their signals, this patch changes that so
that the interrupt signal is only on when the event
happens. The interrupt will be latched into
the interrupt status register anyway, so keeping it
high for (in worst case) one clock cycle is enough.
stekern 4701d 10h /
20 root 5498d 22h /
19 root 5554d 23h /
18 Added old uploaded documents to new repository. root 5555d 02h /
17 New directory structure. root 5555d 02h /
16 Fixed a bug in the IN-FIFO - 18 bit samples where not alligned correctly. rudi 7862d 20h /
15 Updated copyright header. rudi 7919d 07h /
14 Fixed a bug reported by Igor. Apparently this bug only shows up when
the WB clock is very low (2x bit_clk). Updated Copyright header.
rudi 7919d 07h /
13 Changed the datasheet and STATUS.txt rudi 7919d 07h /
12 - Added defines to select fifo depth between 4, 8 and 16 entries. rudi 8111d 10h /
11 - fixed spelling rudi 8117d 08h /
10 - Fixed the order of the thrash hold bits to match the spec.
- Many minor synthesis cleanup items ...
rudi 8117d 09h /
9 *** empty log message *** rudi 8137d 04h /
8 Simulation Makefile rudi 8137d 04h /
7 Added test bench for public release rudi 8137d 05h /
6 - Removed RTY_O output.
- Added Clock and Reset Inputs to documentation.
- Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
rudi 8324d 05h /
5 Added Directory Tree Description to README file rudi 8327d 05h /
4 - Changed to new directory structure rudi 8331d 06h /
3 This commit was manufactured by cvs2svn to create tag 'start'. 8407d 11h /
2 Initial Checkin rudi 8407d 11h /
1 Standard project directories initialized by cvs2svn. 8407d 11h /

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