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Subversion Repositories bustap-jtag

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Rev Log message Author Age Path
22 ash_riple 3761d 12h /
21 ash_riple 3761d 14h /
20 Added support for 32bit Address bus. ash_riple 3761d 14h /
19 Minor changes. ash_riple 4175d 08h /
18 Added support for Xilinx Chips.
Added support for AXI4-Lite bus. Can be used as an XPS IP.		 ash_riple 4175d 09h /
17 Added unreachable trigger condition "@WR & @RD" checking. ash_riple 4421d 12h /
16 Released version 2.2. ash_riple 4443d 12h /
15 Released version 2.2. ash_riple 4443d 12h /
14 Changed dec to hex value of triggerPnum. ash_riple 4444d 03h /
13 Added minor syntax changes and Linux environment simulation script. ash_riple 4444d 08h /
12 Added timing information to the capture content. ash_riple 4444d 16h /
11 Added pre-trigger capture. ash_riple 4445d 08h /
10 Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure. ash_riple 4450d 13h /
9 Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do".
Virtual JTAG stimulus can only be entered statically before simulation starts.
FIFO operation can be simulated dynamically while simulation is run.		 ash_riple 4451d 08h /
8 Added fault handling of wrong input length in the GUI. ash_riple 4455d 08h /
7 Added references related to "Bus Monitor". ash_riple 4455d 12h /
6 Updated to 2.1. New features added as in doc/Revision History.txt. ash_riple 4456d 08h /
5 Created code base for 2.x development.
Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.		 ash_riple 4459d 09h /
4 Created tag for original source code. Version 1.0. ash_riple 4459d 11h /
3 Added original article. ash_riple 4459d 11h /
2 Checked in working code base. ash_riple 4463d 08h /
1 The project and the structure was created root 4463d 22h /

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