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URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] - Rev 333

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Rev Log message Author Age Path
333 update TODO hellwig 2765d 22h /
332 update COPYING hellwig 2826d 22h /
331 machine monitor: init kbd and dsp only if explicitly requested hellwig 2827d 12h /
330 sim/getline/testgl.c: return type of main() changed to int hellwig 2827d 12h /
329 lcc/lburg/gram.y: prototype for yylex() added hellwig 2827d 12h /
328 lcc/etc/lcc.c: return type of main() changed to int hellwig 2827d 12h /
327 flag -m32 in compilation of vcdchk deleted hellwig 3094d 23h /
326 RAM simulation access times set to realistic values hellwig 3205d 17h /
325 memory speed measurement for new controller added hellwig 3214d 08h /
324 README updated hellwig 3214d 09h /
323 memspeed renamed to memspeed-1 hellwig 3214d 09h /
322 README updated, Makefile added hellwig 3214d 21h /
321 README updated hellwig 3214d 22h /
320 README updated hellwig 3215d 18h /
319 memory controller 2, FPGA realization hellwig 3215d 22h /
318 memory controller 1, FPGA realization hellwig 3215d 22h /
317 README updated hellwig 3216d 13h /
316 README added hellwig 3216d 16h /
315 README added hellwig 3216d 17h /
314 memory controller simulation 2 hellwig 3216d 19h /
313 memory controller simulation 1 hellwig 3216d 20h /
312 memory controller simulation 0 hellwig 3216d 21h /
311 README updated hellwig 3216d 22h /
310 verilated mc implementation with and without trace hellwig 3217d 19h /
309 multicycle simulation of ECO32, using Verilator hellwig 3218d 19h /
308 multicycle design, suitable for being verilated hellwig 3218d 23h /
307 several tests got duration.dat files hellwig 3219d 13h /
306 tool to show display output added hellwig 3219d 20h /
305 tool to show serial output added hellwig 3219d 21h /
304 Makefile updated hellwig 3222d 08h /

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