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[/] - Rev 23

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Rev Log message Author Age Path
23 better - root cause of synth issues was switch de-bounce. Working through remaining tests stvhawes 3255d 20h /
22 mixed rising_edge / falling_edge logic removed stvhawes 3261d 12h /
21 flakey sim bugs (1/10 test 2 fails) stvhawes 3261d 14h /
20 search_control_sim prepped stvhawes 3268d 09h /
19 search_control is up for simulation (ghdl) - tidied extra testbenches stvhawes 3275d 08h /
18 search_control is up for simulation (ghdl) stvhawes 3275d 09h /
17 persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id stvhawes 3280d 19h /
16 minor fixes to search_control test bench stvhawes 3287d 06h /
15 adding in search_control and testbench stvhawes 3288d 10h /
14 search_item_wrapper bench debugged stvhawes 3294d 07h /
13 test bench for search_item stvhawes 3297d 11h /
12 wrapper test for search_item stvhawes 3302d 21h /
11 multiplex searh item added stvhawes 3303d 13h /
10 split source files to sime and rtl stvhawes 3317d 12h /
9 highlevel block diagram added stvhawes 3318d 09h /
8 sim sequence error fixed, so 20% success -> 100% success for unit test on fpga stvhawes 3318d 11h /
7 split clock/byte_ready and fix logic stvhawes 3323d 05h /
6 fixing synthesizable stvhawes 3324d 13h /
5 fixing synthesizable stvhawes 3324d 18h /
4 developing ideas around unit test / fpga verification stvhawes 3325d 06h /
3 developing ideas around unit test / fpga verification stvhawes 3325d 06h /
2 initial sources, wrappers for regression test harness stvhawes 3336d 08h /
1 The project and the structure was created root 3338d 03h /

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