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Rev Log message Author Age Path
461 Updated to be much stricter about usage. jeremybennett 4897d 07h /
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4897d 09h /
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 4897d 15h /
458 or1ksim testsuite updates julius 4898d 13h /
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4907d 03h /
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4907d 04h /
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4911d 06h /
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4913d 08h /
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4913d 19h /
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4914d 03h /
451 More tidying up. jeremybennett 4917d 23h /
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4918d 03h /
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4920d 00h /
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 4920d 10h /
447 Updates to register order. jeremybennett 4921d 03h /
446 gdb-7.2 gdbserver updates. julius 4921d 22h /
445 gdbserver update to use kernel port ptrace register definitions. julius 4922d 19h /
444 Changes to ABI handling of varargs. jeremybennett 4923d 04h /
443 Work in progress on more efficient Ethernet. jeremybennett 4923d 07h /
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4923d 22h /
441 Changes for gdbserver. jeremybennett 4924d 04h /
440 Updated documentation to describe new Ethernet usage. jeremybennett 4924d 23h /
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4927d 03h /
438 Fix to newlib header and library locations. jeremybennett 4930d 04h /
437 Or1ksim - ethernet peripheral update, working much better. julius 4932d 18h /
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4933d 18h /
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4933d 19h /
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4937d 00h /
433 New single program interrupt test programs. jeremybennett 4938d 02h /
432 Updates to handle interrupts correctly. jeremybennett 4938d 03h /

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